I. Introduction

Unintentional coupling between PCB traces in high-speed digital circuitry can adversely affect both the electromagnetic interference (EMI) and signal integrity (SI) performance of the circuit. Accurate predictions of EMI and /or SI performance, in turn, are based on adequate characterization of the distributed capacitance and inductance associated with the geometrical configuration of the traces. An FEM approach to predict mutual capacitance is described herein and compared with a commercially available code as well as a set of experimental measurements.

Figure 1 represents a cross sectional view of a pair of microstrip traces. The traces each have a width of W, an edge to edge separation distance of S, and are located a distance of h above a solid conducting ground plane. The length of the traces refers to the dimension perpendicular to the plane of the figure.
 An FEM based numerical code was developed and has been used to predict the mutual capacitance per unit length, , between the two traces shown in Figure 1. Given a sufficiently large length-to-width ratio for the traces, the problem can be reasonably approximated with a two-dimensional model. The two-dimensional model domain is truncated with an artificial boundary on which an analytical boundary condition was applied [1]. The ground plane is taken as the zero potential reference. With an impressed source of  volts on Trace 1, the induced voltage on the floating susceptable trace, Trace 2, can be found from the solution of the Laplace’s equation for an inhomogeneous dielectric
                        
subject to the following boundary conditions:

V=0 on the ground plane
V= on Trace 1
V=, an unknown constant, on Trace 2
=charge per unit length on Trace 2 = 
where  is the outward normal direction of Trace 2, and the integration path consists of the perimeter of the susceptable trace’s cross section as shown in Figure 1. The charge per unit length on Trace 1, , and the voltage induced on Trace 2, , are computed with the FEM code, and subsequently used to calculate the mutual capacitance, . For symmetric geometries,  is
               

Corroboration of the mutual capacitance prediction was done both experimentally and numerically. To verify the mutual capacitance value experimentally, three test boards as shown in Figure 2 and Figure 3 were constructed. Each test board had four SMA connectors in identical locations and each board included a pair of parallel microstrip traces. The microstrip traces on each board were 45 mils wide, and 1.25 mils thick. The dielectric substrate was 45 mils thick with a solid ground plane on the other side. The trace seperation for the three boards varied from 45 mils to 300 mils.

An HP8753D network analyzer was used to measure the  parameter of the each board by connecting Port 1 to one end of one microstrip trace and connecting Port 2 alternatively to the near end and far end of the other microstrip trace. The remaining part of both traces were terminated in an open circuit. The  curves are shown in Figure 4.

The mutual capacitance can then be determined from S21 as
                   [2]

assuming
                  ,
where is the port impedance of the network analyzer.

The experimentally derived values are compared with the FEM predictions in Table 1. Table 1 also includes the results of a commercial FEM code developed by Ansoft. The commercial FEM code included an adaptive meshing algorithm while the FEM code under development relied on user specified meshing.

Values of mutual capacitance calculated using the numerical models were within 13% of the measured values for all three cases.

 Acknowledgement:

The authors gratefully acknowledge the donation of the FEM tool from Ansoft.