DC power bus design is a critical aspect of high-speed digital circuit designs not only for powering devices, but also to mitigate simultaneously switching noise, which is among the primary sources of EMI and SI problems. There are many issues of concern in power bus design including selecting the dielectric materials and spacing (layer stack-up) between power and ground planes, determining the total value and individual value of decoupling capacitors, and location of SMT decoupling capacitors on the PCB. Though these concerns can be investigated with hardware for a specific design, general design guidelines and numerical modeling tools are desirable. A full-wave integral equation formulation with circuit extraction is used herein. There are a number of advantages in having a suitable equivalent circuit model. For example, the circuit quantities, i.e., current and voltage, are directly useful for investigating SI and EMI problems, the extracted circuit model can be reused for both time- and frequency-domain simulations, and many well-developed SPICE and IBIS models for sources, loads, and transmission lines can be easily incorporated into the power bus model. The modeling tool developed in the UMR EMC Laboratory is denoted herein as CEMPIE ( a Circuit Extraction approach based on a Mixed-Potential Integral Equation formulation ).
A current density
and charge density 
is
induced on the metal plane (arbitrary power layer metallization) as a result
of an incident electric field 
. An integral
equation results when enforcing boundary conditions on the conducting plane
[1], [2]:
, (1)
is the dyadic Green's function for
the vector potential, and 
is the Green's
function for the scalar potential. In this case the Green's functions are
for grounded dielectric slabs [3], and the ground plane is considered to
be of infinite extent. The integral equation is then discretized using
the Method of Moments with a triangular mesh and vetor basis functions
[4],[5]. Further, a mixed-potential integral equation results when assuming
the scalar potential is constant within each triangular cell [6]. This
transformation from an EFIE to a MPIE simplifies the circuit extraction.
The circuit model is extracted from the moment matrix without solving the
matrix equation [5].
As shown in Figure 1, there are four distinct steps modeling a power bus structure in this approach. First, a triangular mesh is generated for the metallization plane of concern, i.e., the power plane, which can be arbitrarily-shaped. A ground plane is assumed infinite and its contribution is incorporated into the Green's functions. The second step is to calculate the Green's functions for an arbitrary layer stack-up. Then, a circuit model is extracted. Once the circuit model is obtained, simulations for various "what if" scenarios can be performed using a SPICE simulator.
Approximately 30 minutes are required to extract a circuit model for a 354-branch, 222-node problem, and 5 hours for a 726-branch, 425-node problem, when using a SUN Ultra workstation with 512M memory and a 250 MHz CPU. An additional 1 hour and 6 hours are needed to calculate |S21| from the extracted circuit model using HP-SPICE in an HP workstation with 64M memory and a 66 MHz CPU for the 354-branch, 222-node problem and the 726-branch, 425-node problem, respectively.
A simple power bus structure was used to illustrate the application of the CEMPIE tool in power bus modeling. As shown in Figure 2, a two-layer board was used with the bottom and top layer representing power and ground layer, respectively. Two ports were specified so that |S21| between them can be investigated. Here |S21| was chosen since it is easily measured, and is related to the transfer impedance |Z21| by [7]
, (2)when |S11|» |S22|»
1 and |S21|» |S12|<<1,
which is the common case for most power bus structures. The Z0
in Equation (2) is the characteristic impedance of the system. The top
layer was discretized into triangular cells. The density of the mesh was
determined by the dielectric constant, dielectric thickness and the maximum
frequency needed to model the power bus [5]. A simple l
/10 rule is not always sufficient. An HP8753D network analyzer was used
to measure the |S21|. The reference planes were at the 3.5 mm
test cable connectors. A simple 12-term error correction model using an
open, short, and load was used in the calibration. Port extention was used
to move the measurement plane to the coaxial cable feed terminals. 
There are totally 1601 measured points (from 30 KHz to 6 GHz) and 401 numerically calculated points (from 50 MHz to 5 GHz). The measured and modeled results are compared in Figure 3, and agree well up to 3 GHz. Even beyond, the modeled result indicates the correct trends. The discrepancies at the high frequencies are due in part to experimental errors, as well as numerical errors from the quasi-static approximation of Green's functions. Discrepancies in the magnitude of resonances also result because skin effect and dielectric losses are neglected. Further, the dielectric constant was assumed constant over the considered frequency range.
References