Location:
Room 23 (second floor, on the right) NYU-Poly Westchester Graduate Center 40 Saw Mill River Road (map)
Hawthorne, New York 10532
ABSTRACT
A single integrated circuit can now contain billions of
transistors and wires within a few square centimeters. Individual
features on the chip are now an order of magnitude smaller than the
wavelength of light used to print them.
The talk will give an introductory overview of the modern IC fabrication
process to show how this astounding feat is achieved using a multi-step
process involving photolithography, chemical mechanical polishing,
etching and ion implantation.
The speaker will then describe some of the key lithographic challenges at these
highly scaled technology nodes and some of the solutions used to
overcome these challenges.
BIOGRAPHY
Dr. Amith Singhee is a Research Staff Member at IBM's Thomas J. Watson
Research Center in Yorktown Heights, NY, driving research in the areas
of memory design for manufacturability and Smart Grid applications. He
has over 10 years of research and development experience in the areas of
circuit optimization, performance modeling, extreme statistics,
variability characterization and modeling, circuit simulation and
physical design.
He has a Ph.D. in Electrical and Computer Engineering
from Carnegie Mellon University and is a winner of several best
dissertation and best paper awards, including the 2008 EDAA Outstanding
Dissertation Award and the 2011 Donald O. Pederson Best Paper Award.
He
spent a couple of years from 2002-2004 developing analog circuit
synthesis tools at Neolinear, and subsequently Cadence Design Systems.
Dr. Singhee has co-authored several papers in top Design Automation
conferences and journals along with two books on statistical methods in
VLSI, and has served on several technical program committees of
conferences/workshops in the area of Electronic Design Automation. He is
an IEEE member.
