IEEE BANGALORE SECTION NEWSLETTER

VOL 8, NUMBER 3, SEPTEMBER 2004

 

Page 3 of 10

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EVENTS DURING QUARTER 3, 2004

 

Student Activities

a) Student Congress

The student members elected by the Section for attending the Region10 Student Congress at Hong Kong have returned and have given a feedback that the event was organized well and well attended. 

 b) Student Branches

i)                   The inaugural function of IEEE Student Branch VVCE, Mysore was held successfully on 11th September 2004. The function was attended by Wg.Cdr.Parthasarathy. The Section gave Rs.5000/- to the Student Branch as seed money.

ii)                  The inaugural function of the IEEE Student Branch at St. Joseph Engineering College, Mangalore was held on 25th September 2004. Shri A.Ravi Kiran and Wg.Cdr. Parthasarathy attended the function. The Section gave Rs.5000/- to the Student Branch as seed money.

iii)                On 25th September 2004, as part of M.I.T Student branch’s technical fest, a half-day Tutorial at Manipal on “Network Security” was arranged by IEEE Bangalore Section through the speaker, Shri Purushottam Goel of Intel.

iv)               A half-day Technical Colloquium was conducted by IEEE Bangalore Section on 25th September 2004 at MIT, Manipal.  Section EXECOM speakers Wg.Cdr Parthasarathy, Mr.A.Ravi Kiran and Mr.V.V.Srinivasan delivered talks on Communication Engineering Topics.

Technical Events

1.     Seminar on “Trends in Telecommunications” by Wng. Cmdr. H. R. Parthasarathy was conducted on 13th August 2004 at IETE seminar hall, Ganganagar, Bangalore.

2.     Tutorial on "Network Security" by Purushottam Goel of Intel was held at MIT, Manipal on 25th September 2004.

 

IEEE Electron Devices and Solid-State Circuits Society Bangalore Chapter

The Bangalore chapter organized some successful technical events during the third quarter of 2004. All these events received excellent response from the technical community.

The major event organized by the chapter was a one day workshop on “Bridging technology and design in nanometer era" on 25th September 2004.  The workshop covered various topics of VLSI such as SoC design challenges in Nanometer node, SoC Platform Architecture, Device trends - Challenges and limitations, Analog/RF integration challenges in SoCs, SoC designs with MEMS, and Analog design challenges in the SoC era. The workshop was targeted at the professionals working in the VLSI field. About 100 participants from various industries in Bangalore attended this workshop. Speakers at this workshop included several recognized experts from both industry and academia. The attendees of the workshop were highly appreciative of the technical content and usefulness of the workshop in their regular work. There were several requests to conduct many such events for the benefit of the professionals and students.

The chapter co-sponsored the 8th VLSI Design and Test Workshops held at Mysore during August 26-28, 2004. The technical program of this workshop included several invited talks by industry and academia experts. In addition more than 50 contributed papers were presented at this conference.

The third event was a seminar by   Dr. Chandu Visweswariah from IBM TJ Watson Center on First-Order Incremental Block-Based Statistical Timing Analysis on 18th August 2004. This talk was well attended by about 50 people from industry and academia. In this presentation, Dr Visweswariah discussed a canonical first order delay model for performing timing verification of digital integrated circuits.