ABSTRACT
If the IC and familiar electronics have been key enablers for the 20th century, then functional circuits will most certainly become a key 21st century enabler. This involves an inevitable transition - already underway - from pure electronics to a blend of electronics, photonics and nano-or micro-scale mechanical systems and subsystems/modules. MOEMs derive their functionality from the miniaturization of optics, electronics and mechanics. One problem that has held back MEMS/MOEMS applications until recently is device packaging, which proved problematic for several years.

IC Packaging broadens its Horizon
The growing demand for faster, portable and miniaturized complex electronic systems, with higher reliability, better performance and lower cost, drive the integration of complete systems in a package (SIP) and novel high-density packaging technologies. Different technological approaches are available to achieve high-density interconnection structures. These approaches are generally based on improvements on existing technologies, such as printed wiring board, co-fired ceramic or thin film technology.

Today, the booming wireless telecommunication market stimulates the development of new packaging solutions. As wireless telecommunication systems are moving rapidly to broadband applications at high frequencies, severe requirements are posed on miniaturization technologies and components used to realize the RF front-end of these systems. A miniaturization and integration technology capable of high frequency and high-quality performance is essential. These conditions apply especially to the realization of integrated inductors.

Fueled by price, performance and size factors, the electronics industry is currently experiencing a movement toward smaller, lighter packages that are more powerful than previous designs. This development amplifies the current trend to replace component interconnection leads with bumps to increase performance and decrease size. The continued development and hastening adopting of area-array devices, including chip-scale packages (CSPs) direct chip attach (DCA) and wafer-level packaging (WLP), is paramount. Specific to level 1 (component assembly) and level 2 (component-to-board assembly) packaging, miniaturization will increase pin counts and decrease interconnect pitches as more functionality is embedded into a shrinking die.

This half day tutorial will discuss the new trends in packaging technologies such as Flip chip, Wafer Level CSP, microBGA, stacked die package and many other technologies. The tutorial will also address the electrical, thermal, mechanical and optical characteristics of these packaging technologies and explore the impact of these on VLSI design and system manufacturing and performance. ****************************************************************************

BIOGRAPHY OF TUTORIAL SPEAKER

Dr. Shankara Prasad is currently the CEO of APT Interactive, a company dedicated to providing e-learning and Knowledge management solutions to semiconductor and microelectronics enterprises.

Dr. Prasad obtained his Ph.D from SUNY, Stony Brook, New York. He has worked at Robert Bosch, Reutlingen, Germany as Packaging Technology Development Manager and International Assembly Operations Manager, Cypress Semiconductor, San Jose, California: Assembly & Packaging Technology Manager and Intel Corp. , Santa Clara, California: Package Reliability Group Leader. Most recently, he was the Director of Engineering and Technology Development at Custom Silicon Configuration Services, CS2, Belgium - a Venture capital funded start up company in Europe for advanced packaging foundry. Involved in Technology acquisition from various sources including former USSR, Japan and Germany. He was a Reviewer of the European Commission Program on Advanced Packaging for Harsh Environments and GaAs packaging technology.

Dr. Prasad has also consulted with more than 25 companies in the USA, Singapore, Philippines, Malaysia, Switzerland, Italy, France, Malta, India, Germany, and Brazil including such major companies such as IBM, Digital, SGS Thomson, Philips, Fairchild, AMP, SID, CP Clare, and Siemens, in the area of advanced packaging design, materials, process, manufacturing and reliability.

He has developed and taught technology seminars in the area of VLSI Packaging and more than 2000 engineers and managers from 27 countries have attended his seminars. Dr. Prasad was awarded 1998 IEEE Award for "Major Educational Innovation in Delivery Methods of VLSI Packaging Education"

Other Professional Activities:

Chairman of two international conferences on Microelectronics & Advanced packaging

Published more than 30 articles in the field of semiconductor packaging, e-learning and knowledge management

Active participant in SEMI Packaging conferences & standards programs

Editor of SEMI Newsletter on VLSI Packaging

Advisor to Center for Electronics Design & Technology, I.I.Sc, India

Chairman IMAPS - India

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IEEE Bangalore Section
TUTORIAL on VLSI Packaging for Mobile Communications Applications
April 21, 2001, Saturday
Bangalore, India
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  Registration Form

NON IEEE Members      Rs. 750=00
Non IEEE Students     Rs. 250=00
IEEE Members          Rs. 400=00
IEEE Student Members  Rs. 200=00

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• Welcome
• Special Address for the Silver Jubilee Year
• Presentation of the 2000 activities report
• Presentation of the 2000 Financial report
• BRV Varadan Memorial Prize awards
• Election to Executive Committee for 2001
• Any other items