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TUTORIALS

MORNING SESSION: 8.30 AM to 12.00 Noon

T1: CHALLENGES IN DESIGNING EMBEDDED SYSTEMS ON CHIP
Dr. C. P. Ravikumar(about the Speaker)
Texas Instruments, Bangalore, India

Abstract: This tutorial will address the challenges and problems design engineers face in designing embedded systems on chip. The motivation for this tutorial is the fact that a large number of companies in India/abroad are engaged in activities related to VLSI design, EDA and Embedded System design. Yet, design engineers, who are mostly people with less than 3 years experience, are rarely exposed to all aspects of VLSI system design. This tutorial attempts to fill this gap.

This tutorial will address Front-end Design issues (including conceptual design, RTL design, software design for embedded SOC, design reuse), Verification issues (functional and formal verification, verification of hardware/software systems, coverage estimation), and Physical Design issues (including layout methodologies, issues in partitioning, floorplanning, placement, routing). Further, issues in Post-layout Verification (challenges in design extraction, static timing analysis, simulation), and issues in Testing will be covered.

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