IEEE Bombay Section
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Thursday, 24th April 2008, 1500 hrs
"Exploring Nanostructures for applications in various domains"
by : Dr. Sangeeta Narendra Kale,
Reader in Electronics, Department of Electronics-Science
Fergusson College, Pune 411 004, India
Venue: Seminar room (next to EE office), Girish Gaitonde Building, Second
floor, EE Department, IIT Bombay
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
Nanostructures have steadily received growing interest as a result of their peculiar properties, ability to organize to form superstructures and applications superior to their bulk counterparts. These materials have potential applications in many areas such as optoelectronics, single electron transistors, catalysis and biomedical applications. As is well known, nanodimensional materials can be realized in two different forms: Firstly, in the form of individual particles or a collection of well-separated particles in colloidal solution; and secondly, 2D and 3D superlattices prepared from tailored nanocrystalline building blocks, which would provide new opportunities to optimize and enhance the properties and performance of conventional devices. The presentation will focus on both these aspects with a glimpse of the work being done in our laboratory. Primary emphasis will be given on manganite-semiconductor heterostructures deposited using Pulsed-Laser deposition system, which have been harnessed for diode-like device applications. La0.7Sr0.3MnO3-SnO2 bilayers deposited on various substrates and their structure-property relationships would be primarily discussed. Using these nanomaterials in their suspension form, work has been done in the area of biomedicine and environmental issues. Manganite nanoparticles have been studied as a cancer hyperthermia agent and semiconductor nanoparticles have been investigated as starch inhibitors for diabetes-control and as a catalyst for dye-degradation in industrial applications (typically ZnO and SnO2, respectively), the results of which will be also presented.
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Monday, 21st April 2008, 1430 hrs
"Characterization for Advanced Semiconductor Technologies"
by : Dr. Subhash Kulkarni, IBM New York
Venue: EE Conference Room
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
This talk will cover both technology and functional characterization for
semiconductor process technologies in the deep nanometer regime. We start
by presenting the scaling landscape for process nodes as we head toward
manufacturable 32 nm. We will motivate the vital role played by
characterization in taking a technology from the laboratory to high volume
high-yield manufacturing. Thereafter we will present important techniques
and tools used to measure as well as diagnose manufacturing defects and
process variations. We will also emphasize the deep understanding required
of device physics and materials processing technologies in order for the
characterization engineer to make timely and actionable process
recommendations.
The seminar will be accompanied by an overview of IBM SRDC by Dr. Madabusi
Govindarajan of IBM Bangalore.
About the Speaker:
Dr. Subhash Kulkarni has worked in the semiconductor process and
characterization areas for the past 25 years, in the Microelectronics
Division of IBM. For the past 6 years he has been responsible for
development and manufacturing, starting with 130 and 90nm foundry
technology nodes. His broad experience covers Bipolar, CMOS Logic/memory,
SOI, eDRAM, and TFT technologies, including FEOL and BEOL process and In
Line Test and Wafer Final Test characterization. He was responsible for
managing yields by driving process actions for 200mm and 300mm Programs
using characterization inputs. He was also the lead engineer responsible
for delivery of eCLipze Server and ASIC hardware.
Dr. Kulkarni holds a Bachelor's from IIT-Bombay and a PhD in Material
Science and Physics, Univ. of Illinois, Urbana. He holds about 20 patents
primarily relating to semiconductor process technology and
characterization.
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Wednesday, 16th April 2008, 1430 hrs
Talk 1"About NEMS/MEMS WORKS LLC"
Talk 2"Nanoscale Self Assembly and Its Applications in Sensing, Memory Devices and
Energy Generation"
by : Prof. Shubhra Gangopadhyay & Prof. Keshab Gangopadhyay,
University of Missouri- Columbia
Venue: EE Conference Room, EE Main Building, First Floor
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
Talk-1:
Prof. Keshab Gangopadhyay, University of Missouri- Columbia
The NEMS/MEMS WORKS LLC. (NEMS) was founded in the State of Missouri in
2004. Recently, the University of Missouri-Columbia (UMC) added the economic
development of the community as one of the missions of the university and it
encourages entrepreneurial activities of the faculty leading to
incorporation of start-up companies. In that spirit, NEMS envisages to
develop Nanotechnology by accessing the best venture-development minds and
resources, development of commercialization plans and fundraising. Through
an agreement with UMC, NEMS will have exclusive licenses to all relevant
technologies developed and owned by the university. Since 2006, the company
has obtained federal Small Business Initiative Research (SBIR) grants to
develop synthesis of several nanomaterials, nanoengineering of processes to
achieve tunability and scaling-up of these methods. Nanosynthesis processes
for several oxidizers and fuels by both bottom-up and top-down methods and
self-assembly and physical mixing (called superthermites) of these
components by will be discussed. The combustion of some of these
nanoenergetic materials can generate shockwaves and one such example will be
presented. These results have already been disseminated for public
information in research journals. The company has an immediate plan to
scale-up the components of these superthermites and manufacture a
microdevice for shockwave generation for biomedical applications such as
drug delivery and cell transfection. The company has a future plan to
diversify in adjacent markets such as surgical tools nanocoatings,
microdevice for single cell adhesion and manufacturing of organosillicate
nnaoparticles and its applications thereof, such as liquid core waveguides
(LCW). Prototypes for some of the microdevices have been developed and
several SBIR proposals have been written to improve these technologies
further. NEMS is also in dialogue with an investment firm- The Incubation
Factory (TIF)- to commercialize the novel products. The company envisages to
add an international component to its research and commercialization
activities.
Talk-2:
Nanoscale Self Assembly and Its Applications in Sensing, Memory Devices and
Energy Generation
by Shubhra Gangopadhyay,
La Pierre Chair, Professor,
Department of Electrical and Computer Engineering,
University of Missouri-Columbia
Our group is currently working on the integration of top down semiconductor
and MEMS processes with bottom up self assembly based chemical synthesis
processes. We have several ongoing research projects in the areas of
biosensors, nanoengineered energetic materials, bulk and thin films with
ordered and random pores and high dielectric constant materials. Here is the
summary of some of the research projects I will discuss.
Microchip-based optical and electrochemical systems for sensing
We are currently working on the micro fabrication of an optical system for
fluorescence detection. Our goal is to fabricate a compact system utilizing
the unique properties of nanoporous materials (low refractive index and
large surface area) to fabricate liquid core waveguides. This system is
currently tested for HIV virus detection. For electrochemical sensing
device, the basic idea of is to use micro fluidic channels and
microelectrodes to realize automatic single cell positioning and
amperometric detection of small amounts of chemicals release such as
catecholamine. We are also fabricating microelectrodes by assembling
graphite nanoparticles and carbon nanotubes on chip.
Novel Nanostructured Energetic Materials
Engineered nano-scale composites show promise for energetic material
applications because of the removal of diffusion barrier resulting in a fast
reaction between fuel and oxidizer. We are currently working on new
approaches for self assembling fuel and oxidizer nanocomposites on microchip
and utilizing semiconductor chip processing for applications such as power
generation, microthrusters and shock waves for nanoparticle based drug
delivery.
Metal Nanoparticle-Dpoed Dielectric Films for Non-Volatile Memory
Applications
Our research is focused on using gold and silver nanoparticles to enhance
the dielectric constant of amorphous HfO2 and Al2O3. Metal nanocrystals of
diameter down to 1nm are incorporated in high-K dielectrics for achieving
non-volatile memories. Nanocrystal based non-volatile memories are discrete
charge storage devices and are strong candidates for replacement of
conventional FLASH memories.
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March 6-8, 2008 IEEE Conference of AI Tools in Engineering
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Thursday, January 31st, 2008, 1600 Hrs
"Recent Development in Generalization Error for
Supervised Learning Problem with Applications
in Model Selection and Feature Selection"
by : Professor Daniel S Yeung,
President IEEE Systems, Man and Cybernetics Society,
President of Machine Learning and Cybernetics Research Institute, Hong
Kong.
Venue: Conference Room, GG Bldg., 2nd floor, IIT Bombay
Jointly with IEEE Systems Man & Cybernetics Chapter,
Departments of Electrical Engineering &
Computer Science and Engineering, IIT Bombay
Abstract:
Generalization error model provides a theoretical support for a
classifier's performance in terms of prediction accuracy. However,
existing models give very loose error bounds. This explains why
classification systems generally rely on experimental validation for
their claims on prediction accuracy. In this talk we will revisit this
problem and explore the idea of developing a new generalization error
model based on the assumption that only prediction accuracy on unseen
points in a neighbourhood of a training point will be considered, since
it will be unreasonable to require a classifier to accurately predict
unseen points "far away" from training samples. The new error model
makes use of the concept of sensitivity measure for an ensemble of
multiplayer feedforward neural networks (Multilayer Perceptrons or
Radial Basis Function Neural Networks). Two important applications will
be demonstrated, model selection and feature reduction for RBFNN
classifiers. A number of experimental results using datasets such as the
UCI, the 99 KDD Cup, and text categorization, will be presented.
About the Speaker:
Daniel S. Yeung (Ph.D., M.Sc., M.B.A., M.S., M.A., B.A.) received his
Ph.D. in Applied Mathematics from the Case Western Reserve University.
He is the President of the IEEE Systems, Man and Cybernetics (SMC)
Society, a Fellow of the IEEE and an IEEE Distinguished Lecturer. He
received the Ph.D. degree in applied mathematics from Case Western
Reserve University. In the past, he has worked as an Assistant Professor
of Mathematics and Computer Science at Rochester Institute of
Technology, as a Research Scientist in the General Electric Corporate
Research Center, and as a System Integration Engineer at TRW, all in the
United States. He was the chairman of the department of Computing, The
Hong Kong Polytechnic University, Hong Kong, and a Chair Professor from
1999 to 2006. He is now the President of the Machine Learning and
Cybernetics Research Institute based in Hong Kong. His current research
interests include neural-network sensitivity analysis, data mining,
Chinese computing, and fuzzy systems. He was the Chairman of IEEE Hong
Kong Computer Chapter (91and 92), an associate editor for both IEEE
Transactions on Neural Networks and IEEE Transactions on SMC (Part B),
and for the International Journal on Wavelet and Multiresolution
Processing. He is a member of the Board of Governor, a Vice President
for Technical Activities, and a Vice President for Long Range Planning
and Finance for the IEEE SMC Society. He co-founded and served as a
General Co-Chair since 2002 for the International Conference on Machine
Learning and Cybernetics held annually in China. He also serves as a
General Co-Chair (Technical Program) of the 2006 International
Conference on Pattern Recognition. He is also the founding Chairman of
the IEEE SMC Hong Kong Chapter.
His past teaching and academic administrative positions include a Chair
Professor and Head at Department of Computing, The Hong Kong Polytechnic
University, the Head of the Management Information Unit at the Hong Kong
Polytechnic University, Associate Head/Principal Lecturer at the
Department of Computer Science, City Polytechnic of Hong Kong, a tenured
Assistant Professor at the School of Computer Science and Technology and
Assistant Professor at the Department of Mathematics, both at Rochester
Institute of Technology, Rochester, New York.
He also held industrial and business positions as a Technical
Specialist/Application Software Group Leader at the Computer Consoles,
Inc., Rochester, New York, an Information Resource Sub-manager/Staff
Engineer at the Military and Avionics Division, TRW Inc., San Diego,
California, and an Information Scientist of the Information System
Operation Lab, General Electric Corporate Research and Development
Centre, Schenectady, New York.
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Tuesday, January 29th, 2008, 14.30 Hrs
"Spoken Term Detection: An Old Problem with A New Twist"
by : Zak Shafran,
Assistant Professor,
OGI School of Science & Engineering,
at OHSU Portland, USA
Venue: Conference Room, GG Bldg., 2nd floor, IIT Bombay
Jointly with Communications Society Bombay Chapter and IIT Bombay
Abstract:
Spoken term detection can be viewed as a new incarnation of the old
keyword spotting problem, but this time with a need for scalable
algorithms to process massive spoken archives, like a "Google for
voice". This talk will provide an overview of the task, including the
definition, the metric and the key challenges, as well as the approach
we have adopted in the system fielded by us in collaboration with SRI in
the 2006 NIST Spoken Term Detection (STD) evaluation. The system uses a
word-based indexing approach, a threshold based on detection theory, and
an STT error model to search for words that are out of vocabulary for
STT. In addition, the talk will also describe the impact of performance
of STT on the STD performance, issues of computational efficiency, and
our ongoing work on query expansion in this domain.
About the Speaker:
Izhak (Zak) Shafran is currently an Assistant Professor at OGI School of
Science & Engineering in Portland, Oregon. His research is largely
focused on modeling speech in the context of large vocabulary
speech-to-text, acoustic modeling, spoken term detection, prosody
modeling, and language recognition. The application areas of his
research ranges from government tasks to medical domain. Before joining
OGI, he was a research faculty at the Center for Language and Speech
Processing at Johns Hopkins University. After his doctoral from
University of Washington, he was a member at AT&T Labs Research in the
Speech Algorithms Group, during which he spent a summer at LIMSI
(France) as a visiting professor at University Paris Sud.
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Friday, January 18th, 2008, 17.30 Hrs
"WiMAX– A Key Wireless Broadband Technology"
by : Dr. Suresh Borkar,Department of ECE, Illinois Institute of Technology, Chicago, USA
Venue: Conference Hall, BSNL Complex, 2nd Floor, A” Wing, Juhu Danda, Santacurz - West, Mumbai – 400 054
Jointly with Communications Society Bombay Chapter and IETE Mumbai Centre
Abstract:
* Framework
– Content
* Broadband Wireless Landscape
– Applications and Requirements
– Introduction to Communications and Networking
* WiMAX Standard
– Architecture
– Network Operations and Management
– Inter-relationship with other technologies
* Network Evolution
– Migration to future networks
* Concluding Remarks
– Application to India Environment
– Summary
About the Speaker:
* 1982-Present: Adjunct Faculty Member and Senior Lecturer, Dept of
ECE, Ill Instt of Tech, Chicago
– Development of Advanced and Inter-disciplinary Courses
* 1980 – 2006: Alcatel-Lucent (formerly AT&T, Lucent)
– Director - Mobility / Wireless Development, Integration, and
Delivery
– CTO and Head - Tata-Lucent JV and Lucent India Inc.
– Technical Manager – Telecom Customer Management, Product
Management, Architecture, Development, Integration
– Distinguished Member of Technical Staff - Computer and
Networking Systems Product Management, Architecture,
Development, Integration
* Also with Zenith Radio Corpn and Tata Electric R&D
– Computers, Deflection and Display Systems
* Reviewer / Contributor to IEEE
* Convener, Panel discussion on India Telecom, Oct 2007, IIT(India) -
US Midwest Chapter
* B. Tech (IITD), MS and PhD (Ill Instt of Tech), Chicago
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Friday, January 11th, 2008, 1600 Hrs
"Past and future half-centuries for semiconductor device development"
by : Prof. Hiroshi Iwai, Tokyo Institute of Technology, Japan
Venue: PS Saxena Hall , IIT Bombay
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay Golden Year Celebrations
Abstract:
Electronics is certainly one of the most important technologies emerged in the last century and is expected to further evolve rapidly in the new century. Today, almost all human activities cannot be held without the help of electronics. Electronics started with the invention of vacuum tube about 100 years ago. It developed rapidly with the replacement of vacuum tubes with semiconductor devices in the middle of the last century, and now semiconductor devices are the key for the development of new electronics for future 50 years towards the middle of this century. There have been three aspects for the evolution of semiconductor devices; 1) device structure & operation mechanism, 2) choice of materials, 3) miniaturization of the devices. Already the size of the electronic devices have shrunk more than one million times in the past 100 years from vacuum tube to the most recent CMOS transistors. Now, the miniaturization is approaching its limit, and new paradigm is about to start for the
semiconductor device development. In this talk, past 50 years of the semiconductor device development is reviewed and future 50 years for that is predicted.
About the Speaker:
Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo and worked in the research and development of integrated circuit technology for more than 25 years in Toshiba. He is now a professor of Frontier Collaborative Research Center and Dept. of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Japan. Since joining Toshiba, he has developed several generations of high density static RAM's, dynamic RAM's and logic LSI's including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high-speed bipolar transistors. He has authored and coauthored more than 200 papers.
He has served on many committees of conferences and editors of journals, as well as a member of many evaluation committees of public organizations. For example, the President of the IEEE EDS, an elected member of the IEEE EDS AdCom, an editor of IEEE EDS Newsletter, a guest editor of IEEE Trans. on Electron Devices, and an editor of the Proceedings of ECS Symp. on ULSI Process Integration. He is now the Jr. Past President of the IEEE EDS. He is also a consultant professor of Huazhong University of Science and Technology, Wuhan, China.
His awards include Local Commendation for Invention from Japan Institute of Invention and Innovation (1990, 2005), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul Rappaport Award (1994), IEICE ES Electronics Award (1998), IEEE EDS J.J.Ebers Award (2001), and JSAP Award for the best paper (2002).
His current research interests are Nano CMOS and Emerging Technologies: Highk gate insulator, Si Nanowire MOSFETs, CNT FETs, plasma doping for ultra-shallow junctions, Ni salicide, RF CMOS modeling, and Ge transistors.
Dr. Iwai is, a Fellow of IEEE, a member of Electrochemical Society, a Fellow of the Japan Society Applied Physics, a Member of the Institute of Electronics, Information and Communication Engineers of Japan, and a Member of the Institute of Electrical Engineers of Japan.
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Wednesday, January 9th, 2008, 14.30 Hrs
"Advanced Logic and Memory Technologies with New
Materials and Structures"
by : Prof. Hiroshi Iwai, Tokyo Institute of Technology, Japan
Venue: EE Seminar Hall, IIT Bombay
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
The Scaling of MOS Technologies has resulted in many unwanted
ill-effects and thereby degrading the performance of the transistors.
Coupled with these problems one has already reached limits of
Gate-insulator Silicon dioxide thickness which is now getting to less
than 0.5 nm.This is like a mono layer of atoms and hence uniform growth
is just ruled out.The search of new MOS gate insulator was essential and
High-K materials are currently being researched with vigor.These
materials allow higher thickness of Gate insulator
without degrading Electrical performance. But their technology is not yet
well within full control and hence the research is needed on many of these
High-K candidates like Silicon Nitride, Aluminum Oxide,Hafnium
Oxide,Zirconium Oxide,Tantalum Oxide and Lanthanum Oxides. Depending upon
the Structure of device for Memories and Logic, being used and the Node of
Technology under consideration, one has to decide upon the High-K
material. The Talk will address some of the issues of growth and suitability of each
of them based on properties of these materials to desired structure.
About the Speaker:
Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo and worked in the research and development of integrated circuit technology for more than 25 years in Toshiba. He is now a professor of Frontier Collaborative Research Center and Dept. of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Japan. Since joining Toshiba, he has developed several generations of high density static RAM's, dynamic RAM's and logic LSI's including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high-speed bipolar transistors. He has authored and coauthored more than 200 papers.
He has served on many committees of conferences and editors of journals, as well as a member of many evaluation committees of public organizations. For example, the President of the IEEE EDS, an elected member of the IEEE EDS AdCom, an editor of IEEE EDS Newsletter, a guest editor of IEEE Trans. on Electron Devices, and an editor of the Proceedings of ECS Symp. on ULSI Process Integration. He is now the Jr. Past President of the IEEE EDS. He is also a consultant professor of Huazhong University of Science and Technology, Wuhan, China.
His awards include Local Commendation for Invention from Japan Institute of Invention and Innovation (1990, 2005), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul Rappaport Award (1994), IEICE ES Electronics Award (1998), IEEE EDS J.J.Ebers Award (2001), and JSAP Award for the best paper (2002).
His current research interests are Nano CMOS and Emerging Technologies: Highk gate insulator, Si Nanowire MOSFETs, CNT FETs, plasma doping for ultra-shallow junctions, Ni salicide, RF CMOS modeling, and Ge transistors.
Dr. Iwai is, a Fellow of IEEE, a member of Electrochemical Society, a Fellow of the Japan Society Applied Physics, a Member of the Institute of Electronics, Information and Communication Engineers of Japan, and a Member of the Institute of Electrical Engineers of Japan.
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December 16th -20th, 2007
IWPSD -International Workshop on the Physics of Semiconductor Devices
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Tuesday, December 18th, 2007, 1500 hrs
"Heterogeneous Wireless Communication Devices-Present and Future"
by : Dr Vijay Nair
Venue: Sameer, IIT Bombay
Jointly with Communications Society Bombay Chapter and SAMEER
Abstract:
Convergence of communication and computing technologies is rapidly changing the requirement of wireless devices. While wireless wide area network (WWAN) based on cellular radios was evolving, a new set of wireless LAN networks which are fundamentally different from cellular networks emerged. Devices for applications in the wireless LAN networks (WLAN), wireless personal area networks (WPAN) and wireless metro area networks (WMAN) are being deployed in increasing numbers. Bluetooth and Ultra Wideband (UWB) technologies have been introduced for high-bandwidth wireless connectivity in personal area networks. Location identification technologies like GPS are getting integrated with wireless products as well. There is no doubt that tomorrow’s network environment will be extremely heterogeneous.
However, network heterogeneity also brings with it enormous challenges, as devices will have to be extremely capable in order to intelligently roam around heterogeneous networks operating under a wide range of protocols. As network diversity increases the important challenges of the future communication devices will be coexistence, interoperability and seamless transfer among networks. The vision for ubiquitous computing sees a computational environment where a computer makes decisions and adapts its behavior without being explicitly asked to do so.
This talk will elaborate the vision, the attributes and technical challenges of heterogeneous wireless communication system. In particular advancements of RF component technologies from antennas to baseband ICs will be elucidated. The evolution of different standards and their impact on the mixed network communication will also be discussed.
About the Speaker:
Vijay joined Intel Corporation in September of 2003. He currently leads a team researching in novel antennas and the integration of antennas into RF front-end modules for mixed network radio applications. His research areas included RF and Microwave devices, monolithic ICs, and wireless subsystems.
Before joining Intel, he was with Motorola Inc. While at Motorola, he held various positions including Research Manager of RF Technologies Group and Fellow of Member Technical Staff at Motorola Labs. His group at Motorola developed low power devices, high efficiency power amplifiers, and MMICs for communication applications. He was Motorola’s technical lead for the collaborative research with the University of Florence, Italy, on the development of multifunctional quantum MMICs and he also led a collaboration with Arizona State University in active integrated antenna research. His work at Motorola was highlighted by his receiving of Motorola’s “Distinguished Innovator” award, Gold Quill award and “Product & Process Technology” award.
Vijay holds fifteen (15) US patents. He has published over hundred (100) papers in refereed journals and presented papers in many international conferences and workshops. He has written several chapters for technical books and has co-authored a book titled “RF and Microwave Circuit and Component Design for Wireless Systems”.
The IEEE - Phoenix Section elected Vijay as the “Senior Engineer of the year-1998”. He was elected as an IEEE Fellow in 2000 in recognition of his work in the development of low power device and integrated circuits. He was elected by MTT society as “Distinguished Microwave Lecturer” for a three year term starting January 2007. He is a member of IEEE Microwave Theory and Technique Society (MTT-S), the Communication Society, Antenna and Propagation Society. He is currently the chairman of Meeting and Symposia committee of MTT Society’s Administrative Committee. He served as the Technical Program Committee Chairman of IEEE International Microwave Symposium (IMS2001), 1997 IEEE RFIC Symposium and 1997 IEEE Vehicular Technology Symposium. He is a member of the Advisory Board and Steering Committee of the RFIC symposium. He also serves as a member of the Technical Program Committee of the IEEE International Microwave Symposium (IMS). He served as the vice chair of the MTT-S publication committee, guest editor of MTT-S Transactions, and as a member of Editorial Board of John Wiley & Son’s publications. He has been the Chairman of RF Components and Subsystems Technical Working Group of the National Electronics Manufacturing, Inc. (NEMI) since 1998. He also serves as the Chairman of US National Committee-Commission A of the International Union of Radio Science (URSI). He holds a masters degree in Physics and in Electrical Engineering from University of Minnesota.
- "Annual General Body Meeting"... Notice...Sunday 16th December 2007
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Saturday, September 22nd, 2007, 1530 hrs
"Telecom Operations Support Systems (OSS) - An Overview"
by : Mr. Aiyappan Pillai, VSNL
Venue: Usha Mittal Institute of Technology (UMIT), SNDT University, Santacruz (W)
Jointly with Communications Society Chapter of IEEE Bombay Section
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Wednesday, August 8th, 2007, 1530 hrs
"Related-Key Statistical Cryptanalysis"
by : Dr. Poorvi Vora,
Department of Computer Science,
George Washington University
Venue: KReSIT Seminar Hall
(Seminar to be broadcasted live to CDEEP
Remote Centers)
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
We will present a model for statistical cryptanalysis that treats
statistical key-recovery attacks as communication over a low capacity
channel, where the channel and the encoding are determined by the cipher
and the specific attack. A new attack, related-key recovery, corresponds
to the use of a concatenated code over the channel. Unlike classical
related-key attacks such as differential related-key cryptanalysis, this
attack does not exploit a special structural weakness in the cipher or key
schedule, but amplifies the statistical weakness exploited in the basic
single key recovery. We show that this attack is more efficient than the
single-key-recovery attack in a sense made more precise in the talk. The
practical implications of this result are demonstrated through experiments
on reduced-round
DES.
This is joint work with thesis master's student Darakhshan Mir. Initial
work on this subject was presented at ISIT '06. The ideas are motivated by
related work described in IEEE Trans. Info. Theory Aug '07, Indocrypt '04
and ISIT '03
About the Speaker:
Poorvi Vora is Assistant Professor in the Department of Computer Science
at George Washington University. Her current areas of interest are
cryptology, electronic voting and game theory. She has a Ph.D. (1993) and
M.S. (1988) in ECE from North Carolina State University, an M.S. (Math.,
1990) from Cornell University, and a B.Tech (EE, 1986) from IIT Bombay.
Before GWU, she spent eight years at Hewlett-Packard, where she worked on
digital cameras, watermarking and counterfeit deterrence.
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Tuesday, 10th July 2007, 1130 hrs
"Technology progress in advanced gate stack and reliability issues"
by : Rino Choi, Project manager in Electrical Characterization and
Reliability, SEMATECH
Venue: EE Conference Room, IIT Bombay
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
In the presentation, the efforts to extend the lifetime of CMOS technology will be overviewed and their impact on the device performance/reliability will be summarized. After 30 years of aggressive downsizing of transistors, geometrical scaling has clearly reached fundamental material limits, and is now in the era where further scaling can be realized mainly by new materials and/or device architecture.
Traditional gate stacks based on SiO2 and poly-Si are now being replaced by high-k and metal gates. The near term approach to extend CMOS lifetime is to import new gate stack materials such as high-k dielectrics and metal gate electrodes in to traditional CMOS device structures. Recent reports show that the major technical issues impeding the implementation of alternative gate stack materials have been solved. In this presentation, major process and integration approaches and issues will be introduced and the reliability status of the-state-of-the-art devices from this approach will be summarized. This application of new materials brought unique electrical characterization challenges which require different test methodologies for correct assessment. The degradation mechanisms and models are also different from the conventional ones used for silicon based devices. By applying electrical characterization techniques with high time and spatial resolution (in particular, pulsed Id-Vg measurements in the nanoseconds range, variable frequency charge pumping, etc.) along with profiling of the stack composition using high resolution EELS, XPS, ESR, etc., coupled with ab initio modeling of the dielectric atomic structures, electrically active defects have been identified and physical models for device life-time evaluation were developed.
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Monday, 9th July 2007, 1430 hrs
"Overview of R&D in Micron - Is there really that much "room at the bottom"?"
by : by Chandra Mouli, Senior Fellow & Manager R&D Devices Group, Micron Technology Inc., USA
Venue: EE Conference Room, I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter and IIT Bombay
Abstract:
This presentation will give an overview of Micron's corporate R&D division, which develops next generation semiconductor process/devices for three major product segments - DRAM, Flash and CMOS Image Sensors.
Micron's DRAM and Flash components are used in today's most advanced computing, networking, and communications products,including computers,workstations, servers, cell phones, wireless devices, digital cameras,andgaming systems. Micron is one of the world's leading CMOS image sensor solutions provider for mobile handset camera markets.
Second half of the talk will focus specifically on some of the common challenges in these technologies - as devices are scaled down well into nanoscale features. Practical issues in integrating new materials will be outlined and major concerns related to device fluctuations,variations in characteristics - at the atomic level and their
macroscopic manifestations - will be discussed.
About the Speaker:
Chandra Mouli is with Micron Technology Inc, Boise, Idaho. He is
currently a Senior Fellow and Manager of the Device Analysis Group in
R&D
with responsibilities in the area of advanced device
characterization and reliability analysis, test structure design and
layout, process/device modeling - for all technologies under
development
in R&D. He received his undergraduate degree in Physics and ME
from the
Indian Institute of Science in Bangalore, India and Ph.D (EE) from the
University of Texas at Austin in 1990. He was with Texas Instruments
for
couple of years before joining UT/Austin. He is a senior member in IEEE
and has served in technical committees for various conferences,
including IEDM, SISPAD, IRPS and is currently a member of the ITRS-2007
roadmap committee.
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Tuesday , 26th June, 2007, 1100 hrs
"An Overview of IEEE Computer
Society and Research in
Computer Vision at the University of South Florida."
by : Prof. Rangachar Kasturi, IEEE CS President-Elect
and D W Hood Professor and Chair of Dept of CS Engg, Univ of South
Florida, Tampa.
Venue: KReSIT Seminar Hall, I.I.T. , Powai , Mumbai
Jointly with IIT Bombay
(Lecture to
be broadcast live to CDEEP Remote Centers)
Abstract:
I
will present an overview of IEEE Computer Society's many programs
during
the first half of the talk. In the second half I will present a brief
introduction to several ongoing research projects in Computer Vision at
the University of South Florida. These include text detection in video,
collision avoidance for aircraft navigation, and performance evaluation
of
video object detection and tracking algorithms.
About the Speaker:
Rangachar Kasturi received his BE
(Electrical) degree from Bangalore University, India in 1968 and MSEE
and Ph.D. degrees from Texas Tech University in 1980 and 1982,
respectively. He was a professor of
Computer Science and Engineering and Electrical Engineering at the
Pennsylvania State University during 1982-2003 and was a Fulbright
Scholar during
1999. Dr. Kasturi has been elected to serve as the 2008 President of
the IEEE Computer Society. He was the President of the International
Association for Pattern Recognition (IAPR) during 2002-04. He has
served as the editor-in-chief of the IEEE Transactions on Pattern
Analysis and Machine Intelligence and the Machine Vision and
Applications journals. Dr.
Kasturi is a Fellow of the IEEE and a Fellow of IAPR. He has received
the Penn State Engineering Society Premier Research Award and has been
inducted into the Texas Tech Electrical Engineering Academy. His
research
interests are in computer vision and pattern recognition. He is an
author of the textbook, Machine Vision, and has published numerous
papers and research reference books. He has directed many research
projects in document
image analysis, video sequence analysis and biometrics. In
particular, he is directing a project that evaluates research progress
in detection and tracking of faces, people, text, and vehicles in video
sequences.
-
Thursday , 17th May,
2007, 1600 hrs
39th WORLD TELECOMMUNICATION AND INFORMATION SOCIETY DAY
" Connecting the Young: the opportunities of ICT "
by : Ms. Sujata Dev Managing Director & CEO, Time Broadband
Services Pvt. Ltd.
Venue: : Western Railway Conference Hall, Second Floor, HQ
Office, Churchgate , Mumbai 400 020
Jointly with IETE Mumbai Centre, IRSTE Mumbai Chapter, IET
Mumbai Networks, & BESI Mumbai Chapter
-
Tuesday, 24th April 2007, 1430 hrs
"Microprocessor Platform and Circuit Challenges in the Era of Tera
Scale Computing"
(The talk will cover the what and why of Tera scale computing and briefly go over the platform and circuit technologies needed to get there along with an
overview of the research going on at Intel, Bangalore.)
by : Ms E Vasantha, Head Corporate Technology Group, Intel, Bangalore
Venue: EE Conference Room, EE Department, IIT Bombay
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
About the Speaker:
Vasantha Erraguntla received her B.E in Electrical Engineering from Osmania University, India and an M.S. in Computer Engineering from University of
Louisiana. She joined Intel in 1991 to be a part of the first Teraflop machine design team and worked on its high-speed router technology. In 1995, she joined Intel's Design Technology team that was responsible for validating performance verification tools for high-speed designs. Since 1997, Vasantha has been engaged in a variety of advanced prototype design activities at Intel Laboratories, implementing and validating research ideas in high performance, low power circuits and high speed signaling. Most recently, since June 2004, Vasantha has been heading Corporate Technology Group's Bangalore Design Lab to facilitate world-class circuit research and silicon prototype development. Vasantha has co-authored 7 papers and has 6 patents pending. She is also a member of IEEE
-
Thursday, 12th April 2007 , 1430-1530 hrs
"High Mobility CMOS Germanium CMOS:"Myths and legends"
by : Prof. Kirshna C. Saraswat, Dept of EE, Stanford University
Venue: EE SEMINAR HALL, IIT Bombay
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
Diminishing improvement in the on current (ION) and increase in off current (IOFF) may limit the scaling of bulk Si CMOS. A channel material with high µ and therefore high injection velocity (?inj) can increase ION and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs and increasing the strain provides a viable solution to scaling. However, looking into future scaling of nanoscale MOSFETs it becomes important to look at higher mobility materials, like Ge and III-V together with innovative device structures which may perform better than even very highly strained Si. It is believed that heterogeneous integration of the high mobility materials on Si with novel device structures may take us to sub-20 nm regime. However, one must first answer if high mobility directly translates into high ION and is it possible to get low IOFF especially with low bandgap materials. The high µ materials generally have a lower bandgap (EG), lower effective conductivity mass (m*) and higher dielectric constant (?). Lower EG results in higher IOFF primarily due to band to band tunneling (BTBT) leakage. The main advantage of a semiconductor with a small m* is its high ?inj. However, very high µ materials like InAs and InSb have a very low density of states in the G-valley, which tends to greatly reduce the inversion charge and hence reduced ION. At high gate fields due to quantization the energy levels in G-valley rise faster than L and X-valley, and the current is largely carried in these heavier mass valleys, thus reducing the advantage of high µ. Therefore for both Ge and III-V devices problems of obtaining high on current and leakage need to be solved. Recent results suggest that Ge/Si heterostructures will be suitable to satisfy the p-MOS requirements, however, there appear to be severe limitations of n-MOS. High electron mobility III-V materials could be suitable for n-MOS. However, novel heterostructures will be needed to exploit the promise advantages of Ge and III-V based devices.
About the Speaker:
Prof. Krishna Saraswat is Rickey/Nielsen Professor in the School of Engineering, Professor of Electrical Engineering and Professor of Materials Science & Engineering (by courtesy) at Stanford University. He received Ph.D. in Electrical Engineering from Stanford University in 1974. He serves as the Chair of Stanfords Materials Council and as the Associate Director of the NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing. He also serves on the leadership council of the MARCO Focus Center for Materials, Structures, and nano-Devices. His research interests are in new and innovative materials, structures, and process technology of silicon, germanium and III-V devices and interconnect for nanoelectronics. Prof. Saraswat has graduated more than 50 doctoral students and has authored or co-authored over 500 technical papers, of which six have received Best Paper Award. He is a Fellow of the IEEE, and a member of both The Electrochemical Society and The Materials Research Society. He received the Thomas Callinan Award from The Electrochemical Society in 2000 for his contributions to the dielectric science and technology. He is the recipient of the 2004 IEEE Andrew Grove Award for seminal contributions to silicon process technology.
-
Wednesday, 11th April 2007 , 1430-1530 hrs
"CMOS and beyond"
by : Prof. Kirshna C. Saraswat, Dept of EE, Stanford University
Venue: EE SEMINAR HALL, IIT Bombay
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
It is believed that below the 65 nm node although the conventional bulk CMOS can be scaled, however, without appreciable performance gains. To continue the scaling of Si CMOS in the sub-65 nm regime, innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Examples of novel device structures being investigated are double gate or surround gate MOS and examples of novel materials are high mobility channel materials like strained Si and Ge, III-V semiconductors, high-k gate dielectrics and metal gate electrodes. Heterogeneous integration of these materials on Si with novel device structures may take us to sub-20 nm regime, but will require new fabrication technology solutions that are generally compatible with current and forecasted installed Si manufacturing. Beyond that we will need a set of potentially entirely different information processing and transmission devices from the transistor as we know it, e.g. silicon-based quantum-effect devices, nanotube electronics and molecular and organic semiconductor electronics
About the Speaker:
Prof. Krishna Saraswat is Rickey/Nielsen Professor in the School of Engineering, Professor of Electrical Engineering and Professor of Materials Science & Engineering (by courtesy) at Stanford University. He received Ph.D. in Electrical Engineering from Stanford University in 1974. He serves as the Chair of Stanfords Materials Council and as the Associate Director of the NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing. He also serves on the leadership council of the MARCO Focus Center for Materials, Structures, and nano-Devices. His research interests are in new and innovative materials, structures, and process technology of silicon, germanium and III-V devices and interconnect for nanoelectronics. Prof. Saraswat has graduated more than 50 doctoral students and has authored or co-authored over 500 technical papers, of which six have received Best Paper Award. He is a Fellow of the IEEE, and a member of both The Electrochemical Society and The Materials Research Society. He received the Thomas Callinan Award from The Electrochemical Society in 2000 for his contributions to the dielectric science and technology. He is the recipient of the 2004 IEEE Andrew Grove Award for seminal contributions to silicon process technology.
- Saturday, 31st Mar, 2007, 1700 hrs
"Internet Banking
by Prof. Ward Hanson, Stanford University
Venue: Western Railway Conference Hall, Second Floor, HQ Office, Churchgate, Mumbai
Jointly with IETE, IET and IRSTE
-
Saturday 3rd Mar 2007, "Year
2007 Prof K Shankar Student Paper and Project Contest"
Venue: SPCE, Andheri (West)
The last date for Submitting the papers and Project ideas : Tuesday 27th Feb 2007
The date of presentation of the selected papers and projects : Saturday 3rd Mar 2007
- Tuesday, 27th Feb, 2007, 1230 - 16.30 hrs
Lunch meeting with Directors of Communications Society of IEEE
IEEE Bombay Section has organised a lunch meeting with a high level
team of Directors of the Communications Society of IEEE with special
invitees from the industry for a face to face interaction.
The team comprises of :
Dr Doug Zuckerman
President Elect of the Communications Society, IEEE
Dr Roberto Saracco
CTO, Telecom, Italia
Member Strategic Board of IEEE
Director of Communications Society for Sister Societies, IEEE
Venue : The Lotus Suites, Andheri Kurla Road, Andheri (E), Mumbai between 12.30 to 4.30 pm on February 27, 2007.
- Monday, 26th Feb, 2007, 1430 hrs
"Is there a Future for Telecommunications?"
"Looking into Today's Situation and Challenges Lying Ahead"
by Dr. Roberto Saracco,
CTO, Telecom, Italia
And Member Strategic Board of IEEE
Venue: KReSIT Seminar Hall , I.I.T. , Powai , Mumbai
(Lecture to be broadcasted live to CDEEP Remote Centers)
Jointly with IEEE ComSoc Bombay Chapter and IIT Bombay
Abstract:Technology
evolution is not just fast, to a good extent it is also
predictable. However, the market uptake of technology, the variety of
culture, regulation and individual enterprise strategy can
significantly
change the evolution.
The talk looks into a few technology road maps, storage, processing,
display, sensors, energy, and stimulate thinking on what all that might
mean to the business. In a global world any party is subject to forces
emerging near and far away. At the same time the impact of any single
enterprise can have a global reach.
COMSOC because of its global reach and the breadth of its technology
interest, the variety of players involved in COMSOC life and events can
be a most suitable beacon to understand and influence the evolution.
About the Speaker
Roberto Saracco has over 35 years of experience in
telecommunications. His first research focus was on switching, data
networks and network management. In the last ten years he has shifted
the focus on the economic side of the equation, heading a research team
to analyze the impact of technology evolution on biz and value chains.
In the 1999-2001 he has led a World Bank project to stimulate
enterprise
innovation in Latin America that led to over a hundred innovation
projects. From 2001 to 2004 he led the Future Centre in Venice then he
moved back to the Turin research labs of Telecom Italia to lead a
scenario groups.
In the 1999-2001 he has led a World Bank project to stimulate
enterprise
innovation in Latin America that led to over a hundred innovation
projects. From 2001 to 2004 he led the Future Centre in Venice then he
moved back to the Turin research labs of Telecom Italia to lead a
scenario groups.
-
Tuesday, 13th Feb 2007, 1500 hrs
"The Euclidean Direction Search (EDS) Adaptive Filtering
Algorithm: Theory and Applications"
by : Dr. Tamal Bose,
Director
Center for High-speed Information Processing
Utah State University
Venue: EE Seminar Hall, IIT Bombay
Jointly with COMSOC BOMBAY CHAPTER and IIT Bombay
Abstract:
The Euclidean Direction Search (EDS) adaptive filtering algorithm
minimizes a least-squares cost function by moving in Euclidean coordinate
directions. This talk presents a convergence analysis of the EDS
algorithm, showing that EDS is formally equivalent to Gauss-Seidel
iteration for the solution of linear equations, and that the EDS has zero
excess mean-square error for stationary signals. It is also shown that
the convergence rate is sensitive to the condition number of the
covariance matrix. Several applications of the EDS algorithm are presented
including, system identification, channel equalization, and linear
prediction. In particular, the application of this algorithm is explored
in detail for hyperspectral image processing.
About the Speaker:
Tamal Bose received the Ph.D. degree in electrical engineering from
Southern Illinois University in 1988. After faculty positions at the
Citadel and the University of Colorado, he joined Utah State University in
2000 as an Associate Professor. Currently, he is the Department Head &
Professor of Electrical and Computer Engineering and the Director of the
Center for High-speed Information Processing (CHIP).
The research interests of Dr. Bose include adaptive filtering algorithms,
nonlinear effects in digital filters, and multidimensional system theory.
He is author of the text Digital Signal and Image Processing, John Wiley,
2004. He is also the author or co-author of over 100 technical papers.
Dr. Bose served as the Associate Editor for the IEEE Transactions on
Signal Processing from 1992 to 1996. He is currently on the editorial
board of the IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences, Japan. He also served on the
organizing committees of several international conferences. Dr. Bose
received the 2002 Researcher of the Year award from the College of
Engineering at Utah State University and the 2002 Teacher of the Year
award from the department of Electrical and Computer Engineering. He
received the Researcher of the Year and Service Person of the Year awards
at the University of Colorado at Denver. He also received two Exemplary
Researcher awards from the Colorado Advanced Software Institute. He is an
IEEE EAC program evaluator and a member of the DSP Technical Committee for
the IEEE Circuits and Systems society.
-
Tuesday, 16th Jan 2007, 1430 hrs
"A LOW POWER AND HIGH PERFORMANCE 5 GHz SRAM CIRCUIT
DESIGN WITH IMPROVED CELL STABILITY"
by : Dr. Rajiv V. Joshi, Research staff member at T. J. Watson
research center, IBM
Venue: EE Seminar Hall, IIT Bombay
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
An embedded CMOS static random access memory (SRAM), including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm Partially Depleted Silicon on Insulator (PD SOI) technology. The design features shorter bitlines (16 cells/bitline) along with a thin cell layout and programmable domino read operation. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability. In addition, the SRAM is supplied with multiple supplies: one to the cells, wordline drivers, and level shifters, and the other to the bitline and remaining logic to improve stability and lower power.
About the Speaker:
Dr. Rajiv V. Joshi is a research staff member at T. J. Watson research center, IBM. He received his B.Tech degree from Indian Institute of Technology (Bombay, India), M.S degree from Massachusetts Institute of Technology and Doctorate in Eng. Science from Columbia University, USA. From 1981 to 1983, he with GTE research lab in Waltham, Massachusetts. He joined IBM in Nov. 1983, and since then is working in VLSI design systems, science and technology. He worked on 1.25m NMOS, and CMOS, sub-0.5m CMOS logic, DRAM and SRAM technologies. He developed novel interconnect processes and structures for Aluminum, tungsten and Copper technologies which are widely used in IBM for various sub-0.5m memory and logic technologies as well as across the globe. His circuit related work includes design of register files, registers, latches, L1 caches, Directory, TLB, IO circuits development of physical design tools, and CAD based library generation and circuit designs in SOI technology. He contributed to S/390 Alliance processor design, working in both circuit design and CAD tools. The Alliance G5 chip was a very successful IBM product and Joshi received IBM Research Division Awards for his contributions to it and each of the follow-on processor designs. His 2 GHz SRAM design for G6 received Outstanding technical achievement award. His work also involved design related to SRAM designs, which are widely used across IBM System 390. He has won twenty-nine invention plateau achievement awards from IBM and won two patent portfolio awards for cross-licensing and utilization of his patents in the IBM products. He has received 5 Research Division Awards, and several top 5% and top 30% patent awards (for licensing activities). He won top 5% patent related to steady state timing in SOI. On June 6, 2002 he received Corporate Patent Portfolio award from IBM. He won 2nd corporate patent portfolio award on May 26, 2004. He is a master inventor & key technical leader at IBM research division. He has authored and co-authored over 100 research papers and presented several invited talks. He holds 83 U.S. patents in addition to 40 pending patents. He received the Lewis Winner Award in 1992 for an outstanding paper he coauthored at the International Solid State Circuit Conference. He was instrumental in starting interconnect workshop in early 1980s. He chaired advanced interconnect conferences sponsored by MRS and served as an editor of the proceedings. He is elected as an IEEE fellow for 2002 for contributions to chip metallurgy materials and processes, and high performance processor and circuit design. He is actively involved in IEEE ISLPED (Int. Symposium Low Power Electr. Design) IEEE VLSI design, IEEE Int. SOI conf Program committees. He served as a program chair for Low Power Symposium 2003 and is a general chair for 2004. Joshis patent was the top patent of the decade.
-
Thursday, 4th Jan 2007, 1430 hrs
"Challenges in Advanced Technologies and Enablement"
by : Dr. David Harame IBM Semiconductor Research and Development Center Essex Junction,Vermon
Venue: EE Conference Room, IIT Bombay
Jointly with AP/ED BOMBAY CHAPTER and IIT Bombay
Abstract:
IBM offers advanced SOI and CMOS technologies for servers and digital foundry in and has 45nm and 32nm in development. The CMOS performance roadmap has significant performance issues which are being resolved not by conventional scaling but by innovation. RF/AMS technologies in RFCMOS and SiGe BiCMOS are also developed. RFCMOS will have significant design challenged at advanced nodes. Some of these challenges will be discussed. SiGe BiCMOS is reaching very high performance levels of 300 and 400 Ghz. Scaling issues in SiGe BiCMOS will also be discussed. These technologies are only useful if there are good models and process design kits which address the SOI, CMOS, RFCMOS, and SiGe BICMOS technologies issues. Some key attributes of advanced models and design kits will be discussed.
About the Speaker:
David Harame received the PhD in Electrical Engineering from Stanford University in 1984. He joined IBM in 1984 at the T.J. Watson Research Center in Yorktown Heights NY where he immediately began working on using epitaxial growth techniques in silicon technology to improve device performance. He worked on both SiGe HBTs and SiGe Channel FETs. Dr. Harame was involved with the SiGe HBT work at IBM from its inception and is widely credited for taking the technology from research to manufacturing. During that time he moved from Yorktown to the Advanced Semiconductor Technology Center in Hopewell Junction NY and developed the first fully qualified for manufacturing SiGe HBT process. He then worked on SiGe BiCMOS and moved to Essex Junction Vermont where he developed the first fully manufacturing qualified SiGe BiCMOS process in a large volume fabricator. Dr. Harame now lives in Essex Junction Vermont where he is the Director of IBM's Semiconductor Research and Development Center Enablement Area. This area provides Models and Design Kits for IBM's Semiconductor Technologies. David was the General Program Chair for the 2005 IEEE Bipolar BiCMOS Circuits and Technology Meeting, and the Symposium Organizer for the 2004 and 2006 Electrochemical Society SiGe: Materials, Processing, and Devices Symposium. He has authored or co-authored over 160 articles and holds 16 patents. He is a member of the IBM Academy, an IBM Fellow. and an IEEE Fellow.
-
Tuesday, 2nd January, 2007 , 1400 hrs
"High Mobility Materials and Novel Device Structures for High
Performance Nanoscale MOSFETs"
by Prof. Krishna C. Saraswat, Department of Electrical
Engineering, Stanford University, Stanford
Venue: EE Seminar Hall, IIT ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
- "Annual General Body Meeting"... Notice...Saturday 23rd December 2006
For Past
Events...Click here..
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