| IA-64 And Merced Feature Focus |
Abhishek Addapa, TSEC
Contributing Editor |
IA-64: A new ArchitectureThe IA-64 is an architecture resulting from the collaboration of Intel and HP and its first implementation is Merced. IA-64 is designed to compensate for the complexity of today's CPUs with tighter links between a smarter, more advanced compiler and simpler and faster micro architecture.Need for a new architectureIn the modern CPUs, of the millions of transistors present, very few directly contribute to adding numbers or moving data under the directions of the programs being executed. Far too many are used in rearranging instructions and keeping track of their original code. Many transistors are able to implement many more functional units than CPUs having today, if only hey could be used more productively, a very large percentage of the logic on a microprocessor is dedicated to management functions such as control out of order and speculative execution. Such logic being difficult to design increases the complexity as well as the die area, creating speed-limiting paths. Another problem in today's microprocessors is cache memory, which tells the CPU to work at particular speeds without itself doing any useful work.Architecture enhancements can make cache fundamentally more effective. An innovative architecture can also do more useful work per clock cycle and run at faster clock rates. Features of IA-64 ArchitectureToday's superscalar microprocessors have extensive logic to detect parallelism in the instruction stream and initiate concurrent operations when possible. The IA-64 will pass much of this burden to the compiler to a much greater extent than today's CPUs. The CPU will execute the instruction stream that it is given as fast as it can, knowing the instruction interactions are safe because the compiler made it so. The IA-64 will also included predicated execution and a large |
register set. With more registers a compiler, can use different register subsets to support execution on multiple branch paths, removing the need to analyze independently, because there is lesser need to reuse the registers. Ideally, the compiler and the processor will cooperate to anticipate the use of data so that the cache can be managed more effectively and to anticipate the flow of the program minimizing processor stalls due to unexpected branches. During compilation of the program a compiler can determine quite a bit from the logic of the program, and even more if the language supports advisories from the programmer regarding the programs' expected behavior. The IA-64 will also bend performance/price curve by permitting more internal parallel execution. Compilers that more fully extract parallelism from the source code will achieve the parallelism. Besides this parallelism will be obtained by the addition of explicit parallel notations in the programming languages and new compilers for those languages and explicitly parallelize programs. Limitations of IA-64Despite the innovations, and improvements in the IA-64, it won't sweep away all the competitors instantly. When introduced, Merced will be big and expensive but will get smaller and cheaper over time. All the performance improvements will come with some penalty in the code density. Finally, IA-64 programs will probably have to be re-optimized for each different implementation of the architecture.ConclusionsMerced and IA-64 are arriving and their impact will be profound. There will be significant architectural advances. IA-64 processors will get more work done on each clock cycle through increased on-chip parallelism and will run at faster clock speeds by shifting complexity to the compiler to create a simpler and faster microprocessor. |