Free Space Optical (FSO) and directional RF communications could become a key enabling component for future tactical net-centric systems. Primary advantages of directional networks include high data rates, longer communication range, covertness, LPI/LPD, spatial frequency reuse, and agile topology optimization. A number of critical challenges, however, exist in providing assured connectivity and resiliency for tactical directional networks. In this lecture, an overview of the directional networking technologies will be provided with special focus on gaps in enabling future defense and security net-centric vision, characterization of connectivity and link fragility, and methods for dynamically optimizing topology for maximizing tactical network performance.

Speaker Biography:

Dr. Anurag Dwivedi is a Senior Professional Staff and Section Supervisor at the Communications Systems and Network Engineering Group at the Johns Hopkins University, Applied Physics Lab. in Laurel, MD. Dr. Dwivedi has 17 years of experience in optical and directional RF communications with positions at JHU/APL, Corning Inc., Corvis Corp. (now Broadwing/Level-3), and RHK Inc. (now Ovum). He has performed several studies on optical communications for commercial and military use, and has published more than 40 papers and owns several patents. Areas of his expertise include net-centric architectures, fiber-optic networks, assured connectivity directional RF and free-space optical networks, traffic analysis and forecast, network planning and design, network security, availability, efficiency, utilization, and optimization.

2. Power Electronics and Electron Devices & Solid-State Circuits

The Baltimore Chapters of IEEE Power Electronics and Electron Devices & Solid-State Circuits present:

“A Pictorial Tour of Basal Plane Dislocations and Other Extended Defects in SiC Epitaxy”

Speaker:

Dr. Robert Stahlbush

Naval Research Laboratory

Location:

National Electronics Museum

Pioneer Hall

Date:

Monday, November 9.

The Baltimore Chapters of the Power Electronics and the Electron Devices & Solid-State Circuits Societies are pleased to co-host Dr. Robert Stahlbush of the Naval Research Labs, who will discuss material defect detection and reduction in SiC for the production of power devices. The technical presentation will be preceded by complimentary refreshments. If you plan to attend, please reply to the chapter secretary papotyraj@ieee.org by Friday, November 6 to help us plan accordingly. Regrets need not reply.

AGENDA

5:30 PM Complimentary Refreshments and Social Hour

6:15 PM Seminar by Dr. Stahlbush

7:30 PM Adjourn

ABSTRACT

SiC power devices are replacing some of their Si-based counterparts. The superior material properties of SiC for power devices include 3X larger bandgap, 8X higher breakdown field, and 3X higher thermal conductivity. The emergence of commercially available SiC devices is due in large part to the reduction of material defects which have occurred over the last decade, and further market penetration will depend on continued materials improvements and improved techniques for identifying materials defects which degrade electrical performance.

This presentation surveys epitaxial extended defects, and techniques for detecting and imaging those defects. The survey of detection techniques highlights the newly-developed UltraViolet PhotoLuminescence (UVPL) imaging. The UVPL technique has a number of advantages compared to other methods for examining dislocations and other extended defects. It is non-destructive and images whole wafers, making it an attractive method to screen wafers before fabrication. UVPL is also better than other techniques for tracking defects such as basal plane dislocations (BPDs) through the whole epitaxial thickness.

Of the extended defects shown, an emphasis is placed on BPDs. These defects cause degradation in a number of power devices, including PiN diodes, BJTs, and thyristors, due to stacking faults which originate from the BPDs and degrade the lifetime within the drift region. There is also evidence that BPDs adversely affect device leakage.

Examples of using UVPL to diagnose BPD propagation during epitaxial growth and its use in developing BPD reduction processes are shown. Tracking BPD glide during epitaxial growth has shown that a single BPD can create the defect alternately known as pair arrays or half-loop arrays, which consist of BPD segments in an array which can extend laterally many millimeters. The ability to track BPDs has been instrumental in our development of a method to reduce BPDs by 98% in 8° off-cut wafers using epitaxial growth interrupts, and to understanding BPD reduction in 4° off-cut wafers.

ABOUT THE SPEAKER

Robert Stahlbush is a Research Physicist at the Naval Research Laboratory in the Power Electronics Branch. His research emphasis has been on developing and applying techniques to image dislocations and other extended defects in SiC epitaxy. He has applied these techniques to develop epitaxial growth processes which reduce basal plane dislocation density, and to work with SiC vendors to examine the effects of the material defects on device electrical performance. Results of his research have been reported in over 100 archival journal publications.

DIRECTIONS

The National Electronics Museum is located at 1745 W. Nursery Rd. in Linthicum MD, next to the BWI Marriott.

3. Continuing Education Course for November

Nov 21, 2009 (Sat), 9 am – 1 pm

National Electronics Museum,

1745 W Nursery Rd

Linthicum Heights, MD 21090

Author: Happy Holden

Presenter: Dan Smith

Title:

A PROGRAM of ADVANCED PRINTED CIRCUIT DESIGN:

COST, PERFORMANCE and MINIATURIZATION

Introduction To Advanced PWB Design

Abstract

DESCRIPTION: As finer pitch devices all come into common use, for higher and higher speed logic, the need for advanced printed wiring boards (PWB) is essential - - both as the board and as the package. The presentation will define how to select breakout patterns, circuit routing guidelines, manufacturing process features, microvia-HDI routing issues and techniques for widely accepted fine pitch and BGA components. 1.0 mm, 0.8 mm, 0.65 and 0.5 mm fine-pitch components are the focus of design rules and layer assignments, as well as FPGAs and ASIC to 3200 pins. Some HDI design techniques will emphasize the improved electrical performance and signal integrity. The overview of HDI technology is particularly useful for those not familiar with this technology. Participants are encouraged to bring along their technical questions for discussion.

Content

* The Need for Miniaturization in Design

* IPC Standards for Advanced Interconnects and HDI.

* IPC-2226 Design standards

* The Advantages of blind-vias & HDI with cost comparisons

* Fine-pitch and High-I/O BGA design rules, layer assignment, routing and signal-integrity issues

* Creating Boulevards to Increase Routing Density

* HDI analysis methodology

The Signal and Power Integrity (SI/PI) Performance of Adv. PWBs

DESCRIPTION: High Density Interconnects (HDI) and microvias have benefits for more than just high-density and fine-pitch BGAs. The high-frequency performance of HDI is superior to through-holes (TH) because of its lower inductance / capacitance and elimination of stubs. This presentation highlights the electrical performance benefits of HDI-microvias for not only improvements in signal integrity but reduction in power-supply impedance, resonances, current-density, decoupling capacitors and noise (power integrity). EMI/RFI improvements are also documented in examples for OEM tests.

Content

* HDI Signal Integrity Benefits: Circuit Noise Management

* HDI Power Integrity Benefits: Power Distribution Network (PDN)

* HDI Circuit Card Assembly Benefits: Eliminate 90% of Decoupling Capacitors

* HDI Circuit Card Performance Benefits: Reduce EMI/RFI

Design Features of Higher Density PWBs

DESCRIPTION: This short Seminar looks at advanced wiring technologies for high-density PWBs. Increased density is a factor of line widths, spacings, via diameter and its land, the via architecture and new thin materials that allow for the proper impedances and crosstalk. This Seminar will show how the stackup is determined and show the six (6) design features that allow wiring density of 4X what you would expect from a high-density through-hole PWB. Seven (7) of the most common HDI stackups with their advantages and disadvantages are also highlighted.

Content

* Introduction To High-Density Design Metrics

What determines the ‘best’ high-density stackups

* Via Architectures

Various blind / buried via stackups

* HDI Stackups

Seven of the most used HDI stackups

Case Studies of Design Conversion to Higher Density PWBs

DESCRIPTION: A number of successful multilayer redesigns have been accomplished where advanced technology was employed to reduce the layers, size, and costs by reducing the COMPLEXITY of the former designs. This is a talk to relate the successful Programs used by a number of large Aero/Military and Telecom OEMs to successfully implement High-Density Technologies in their Printed Circuit Board programs. The talk will outline the process and provide several examples as Case Studies.:

Content:

* Critical New HDI Design Technologies

New principles in HDI design that make multilayer simplification possible

* Overview of The Process

How is it possible to reduce layers and/or size?

* Case Studies of Successful TH To HDI Redesigns

Three examples of the successful application of this New Design Process

* Putting It All Together- "Next Step"

How to learn more about “Advanced HDI Technology”

Happy Holden

Author Bio

Happy Holden is the Senior PCB Technologist for Mentor Graphic’s System Design Division in Longmont, CO. He is responsible for advanced and next generation printed circuit technology consulting for Mentor’s customers and MGC engineering. Prior to joining Mentor, he was the Advanced Technology Manager at Westwood Associates and Merix Corporations. He retired from Hewlett-Packard after over 28 years. Mr. Holden formally managed Hewlett-Packard's application organizations in Taiwan and Hong Kong. His prior assignments with HP had been as director of PCB R&D. He holds degrees in Chemical Engineering and Computer Science. He is a member of the IPC, SMTA, IMAPS and the IEEE.

Dan Smith

Presenter Bio

Dan Smith has been involved in all aspects of the PCB design process for over 30 years (Concept through Manufacturing), and over 24 years experience using a variety of EDA tools to design PCBs, Flex, Thick film and ICs . He has worked as a librarian, designer, and programmer at Motorola, US Robotics, and Shure Brothers. Smith is the author of several US software patents that have reduced design process bottlenecks. He has taught internationally, and has co-written training materials, industry articles, and several internal company and IPC standards. He is a member of IPC and the IEEE.

Course applicants please contact Dr. Boris Gramatikov, Director for Continuing EE Education for the Baltimore Section, at:

bgramat@jhmi.edu

Please include your IEEE member number and your present employer in your email.

The website for continuing education for the Baltimore Section is:

http://ewh.ieee.org/r2/baltimore/continuing_education/CEEE.htm

4. Film about Pioneering Inventor

Mechanic to Millionaire: The Peter Cooper Story, a film produced by The Gardner Documentary Group, will cover the life and times of this 19th century pioneering inventor and philanthropist who still speaks to us. Peter Cooper built The Canton Iron Works in Baltimore and cobbled together the first American steam locomotive, the Tom Thumb. From railroad rails he developed the wrought iron I-beam for multi-storied construction, which allowed cities to grow vertically. He was instrumental in financing and laying the first transatlantic cable with Cyrus Field.

With less than a year of formal schooling, he founded The Cooper Union for The Advancement of Science and Art in 1859, realizing his dream of free education for thousands of Americans. The Great Hall, a public auditorium on the lower level, continues to provide a platform for major social movements and politicians advocating reform. It was here that Abraham Lincoln made his celebrated “Right Makes Might” speech that arguably won him his party’s nomination for president. Before being nominated by his party for President, Barak Obama also spoke eloquently about our troubled economy, and later won the top place on the Democratic ticket.

Through his life of invention and philanthropy, we learn about Baltimore’s role in the industrial revolution and Cooper’s vision of social justice. During this recession, his warnings and business advice resonate and bring him back in a fresh and startling way.

James Dilts, historian and noted author of The Great Road: The Building of The Baltimore and Ohio Railroad will join producer/director Janet Gardner for the Q&A discussion following the screening.

5. IEEE USA Employment and Career Services

The IEEE USA Employment and Career Services Committee would like to hear the hot button issues of our members. Members are encouraged to participate in this survey.

http://www.surveymonkey.com/s.aspx?sm=rJoau26ct4T_2fxnNMl7WTAQ_3d_3d

6. Paid Advertisement

The following is a paid advertisement from John P. DeLuca, patent attorney.

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7. Baltimore Region Conferences

The following conferences are planned for Maryland, Washington, DC, and Northern Virginia. This list can be used for planning purposes and also represents potential volunteering opportunities.

Conference: 2009 Grand Challenges in Biomedical Engineering

Conference Dates: 05 Nov - 07 Nov 2009

Location: Bethesda Marriott, Bethesda, MD, USA

Conference: 2009 IEEE 40th Semiconductor Interface Specialists Conference (SISC)

Conference Dates: 03 Dec - 05 Dec 2009

Location: Key Bridge Marriott Hotel, Arlington, VA, USA

Conference Web Site: http://www.ieeesisc.org/

Conference: 2009 IEEE International Electron Devices Meeting (IEDM)

Conference Dates: 07 Dec - 09 Dec 2009

Location: Hilton Baltimore, Baltimore, MD, USA

Conference Web Site: http://www.ieee-iedm.org

Conference: 2009 International Semiconductor Device Research Symposium (ISDRS)

Conference Dates: 09 Dec - 11 Dec 2009

Location: University of Maryland, College Park, MD, USA

Conference Web Site: http://www.ece.umd.edu/isdrs/2009

Conference: 2010 11th Joint Magnetism and Magnetic Materials - INTERMAG Conference

Conference Dates: 17 Jan - 21 Jan 2010

Location: Washington Marriott, Washington, DC, USA

Conference Web Site: http://www.magnetism.org

Conference: 2010 IEEE International Radar Conference

Conference Dates: 10 May - 14 May 2010

Location: Marriott Crystal Gateway, Arlington, VA, USA

Conference Web Site: http://www.radar2010.com/

Conference: 2010 IEEE 37th International Conference on Plasma Sciences (ICOPS)

Conference Dates: 20 Jun - 24 Jun 2010

Location: Marriott Norfolk Waterside, Norfolk, VA, USA

Conference Web Site: http://www.eng.odu.edu/icops2010

Conference: 2010 American Control Conference - ACC 2010

Conference Dates: 30 Jun - 02 Jul 2010

Location: Baltimore Marriott Waterfront, Baltimore, MD, USA

Conference Web Site: http://www.a2c2.org/conferences/acc2010/

Conference: 2010 IEEE 60th Annual Broadcast Symposium (BTS)

Conference Dates: 20 Oct - 22 Oct 2010

Location: The Westin Alexandria, Alexandria, VA, USA

Conference Web Site: http://www.ieee.org/bts/symposium

Conference: 2010 IEEE Frontiers in Education Conference (FIE)

Conference Dates: 25 Oct - 30 Oct 2010

Location: Crystal Gateway Marriott, Arlington, VA, USA

Conference Web Site: http://fie.engrng.pitt.edu/