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MOS Modeling and Parameter Extraction Working Group
The Baltimore Chapter of IEEE Electron Devices and Solid-State Circuits is pleased to be a co-sponsor of the MOS-AK/GSA Workshop. This Compact Modeling Workshop will be held in Baltimore from 9:00 AM - 5:00 PM on December 9, 2009, to be "co-located" with the International Electron Devices Meeting (IEDM) in downtown Baltimore and the International Semiconductor Device Research Symposium at the University of Maryland (ISDRS).
The leading promoter of the workshop technical program is the Global Semiconductor Alliance.
The location of the workshop will be Johns Hopkins University, Homewood Campus, Computational Sciences and Engineering Building (CSEB) Room 17.
Additional information about the workshop, including FREE on-line registration, is available at the workshop home page. Those wishing to present a poster should contact the Technical Program Chair Dr. Andreas Andreou at
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SYNOPSIS
HiTech Forum to Discuss the Frontiers of Compact/SPICE Modeling
MOS-AK/GSA Meetings are aimed at strengthening a network / discussion forum among experts in the field, enhancing an open platform for information exchange related to compact/Spice modeling, bringing people in the compact modeling field together, and obtaining feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme -- frontiers of compact modeling for nm-scale CMOS/SOI circuit simulation.
The specific workshop goal will be to classify the most important directions for the future development of compact models and to clearly identify areas that need further research. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling, IC designers (RF/Analog/Mixed-Signal/SoC) and those starting in that area, and device characterization, modeling and parameter extraction engineers. The content will be beneficial to anyone who needs to learn what is really behind the IC simulation in modern device models.
PROGRAM
9:00 AM - 5:00 PM
Oral Workshop Presentations:
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I. Angelov: "Compact, Equivalent Circuit Models for GaN, SiC, GaAs and CMOS FET"
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A.G. Andreou: TBD
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G. Bersuker: "Physical Models for Transistor Gate Stack Degradation Processes"
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G. Coram: "Verilog-A Standardization and Model Validation"
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B. Iniguez and R. Ritzenthaler: "Advances in SOI Compact Modeling"
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A.S.Kashyap, H. A. Mantooth, T. Vo, M. Mojarradi: "Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design"
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M. Mierzwinski, B. Troyanovsky, and P. O'Halloran: "Practical Considerations for Developing, Debugging, and Releasing Verilog-A Models"
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C.G. Montoro and M. C. Schneider: "CMOS Analog Design Using All-Region MOSFET Modeling"
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M. Reece: TBD
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J. Victory, J. Cordovez, D. Shaeffer: "A Front to Back Process Variation Aware SPICE Based Design System For Arbitrary EM Devices and Shapes"
Panel Discussion:
- Compact Models QA Validation: Still a Challenge?
- Foundries Models vs. Verilog-A Modeling
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