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Meeting Number:   31

May 30, 2013


Energy Efficient and High Performance Architectures for DSP and Communication Applications


Dr. Tinoosh Mohsenin
Assistant Professor
Department of Computer Science and Electrical Engineering
University of Maryland Baltimore County
1000 Hilltop Circle
Baltimore, MD 21250


Thursday, May 30, 2013


5:30 PM:   Snacks
6:00 PM:   Talk begins


National Electronics Museum (NEM)
1745 W. Nursery Road, Linthicum, MD 21090


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Communications systems are becoming increasingly commonplace and appear in a vast variety of applications such as: mobile phones, embedded systems, and medical devices. The need for greater energy efficiency, smaller size and improved performance of these devices demands co-optimization of algorithms, architectures, and implementations. This talk presents several design projects that illustrate the cross-domain optimization.

The design of system-on-Chip (SoC) blocks becomes increasingly sophisticated with emergent communication standards that have large real-time computational requirements. Two such algorithms, Low Density Parity Check (LDPC) decoding and Compressive Sensing (CS), have received significant attention. LDPC decoding is an error correction technique which has shown superior error correction performance and has been adopted by several recent communication standards. Compressive sensing (CS) is a revolutionary technique which reduces the amount of data collected during acquisition and allows sparse signals and images to be recovered from very few samples compared to the traditional Nyquist sampling. While both LDPC decoding and compressive sampling have several advantages, they require high computational intensive algorithms which typically suffer from high power consumption and low clock rates. This talk presents novel algorithms and architectures to address these challenges.

As future systems demand increasing flexibility and performance within a limited power budget, many-core chip architectures have become a promising solution. The design and implementation of a programmable many-core platform performing DSP applications containing 64 cores routed in a hierarchical network is presented. For demonstration, Electroencephalogram (EEG) seizure detection and analysis and ultrasound spectral doppler are mapped onto the cores. The seizure detection and analysis takes 900 ns and consumes 240 nJ of energy. Spectral doppler takes 715 ns and consumes 182 nJ of energy. The prototype is implemented in 65 nm CMOS which contains 64 cores, occupies 19.51 mm2 and runs at 1.18 GHz at 1 V.


Dr. Tinoosh Mohsenin is an assistant professor in the Department of Computer Science and Electrical Engineering at the University of Maryland Baltimore County since 2011. Prior to joining UMBC, she was finishing her PhD at the University of California, Davis. Dr. Mohsenin’s research interests lie in the areas of high performance and energy-efficiency in programmable and special purpose processors. She is the director of Energy Efficient High Performance Computing (EEPC) Lab where she leads projects in architecture, hardware, software tools, and applications for VLSI computation with an emphasis on digital signal processing workloads. She has been consultant to early stage technology companies and currently serves in the Technical Program Committees of the IEEE Biomedical Circuits & Systems Conference (BioCAS), Life Science Systems and Applications Workshop (LiSSA), International Symposium on Quality Electronic Design (ISQED) and IEEE Women in Circuits and Systems (WiCAS).

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