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 Meetings
Past Events:
January 28, 2010
February 25, 2010
March 25, 2010
April 22, 2010
May 27, 2010
July 29, 2010
August 26, 2010
September 16, 2010
September 17, 2010
October 28, 2010
Back to Past Events
| Date: |
January 28, 2010 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
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| Topic: |
Alternate n-type and p-type semiconductor materials for flexible electronics
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| Description: |
A grand challenge in flexible, thin-film-transistor (TFT) circuitry is the development of complementary metal oxide semiconductor (CMOS) circuits. Although flexible digital circuits, flexible sensors, flexible batteries and solar cells have already been demonstrated, the missing technology piece that must be developed is flexible analog circuitry. For example, an operational amplifier will enable the interface to most sensors and actuators, significantly expanding the functionality of flexible electronic systems. In this talk, we will discuss n- and p-type chalcogenide-based materials that can be used as the building blocks for analog CMOS-based circuits. In particular, we will introduce the use of chemical bath deposition as an alternative to deposit these materials and will discuss the correlation between device characteristics and materials properties.
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| Speaker: |
Professor Manuel Quevedo-Lopez
Department of Materials Science and Engineering
University of Texas at Dallas
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| Speaker Bio: |
Manuel Quevedo-Lopez received a Ph.D. degree from the University of North Texas, Denton TX, USA in 2002. He then joined Texas Instruments's Silicon Technology Develoment Group as Member of technical Staff where his research focused on advanced high-k gate dielectric and CMOS isolation technologies. In 2004 He joined SEMATECH in Austin Texas as TI assignee to work on SEMATECH's advanced gate dielectric project. Dr. Quevedo-Lopez is author or co-author of more than 40 publications in peer reviewed journals and 3 US patents issued and 10 more pending.
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| Date: |
February 25, 2010 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
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| Topic: |
NuCo USA presents: Roadmap to a Solar Career
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| Description: |
Demand is growing for employees who have skills in the clean technology arenas, including energy efficiency, water efficiency, renewable energy and clean transportation. Industry estimates indicate continued strong growth in solar energy jobs worldwide. Most of the new jobs will be in marketing and installation of solar photovoltaic and thermal systems, which means they will be located close to end market users of solar systems, thereby being highly beneficial to local economies.
The need for qualified solar electric system installers has been recognized in the USA through the establishment of a national certification program overseen by the North American Board of Certified Energy Practitioners (NABCEP). When most engineers decide to make the leap to the renewable energy industry they find there is no clear path. By working with Industry experts NuCo has developed the training and guidance needed to help you make the transition to a renewable energy career.
Because NuCo Corporation USA was founded by experienced semiconductor engineers, we are committed to training displaced semiconductor industry professionals to find new careers in the Solar / Photovoltaic and green jobs arena. NuCo has developed on-line and hands-on training programs that adhere to NABCEP, ETA and DOE standards and criteria. NuCo is partnering with local colleges to build 'hybrid' training classes that will rapidly educate displaced workers so they can find a green job.
Let NuCo show you the roadmap to a solar career.
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| Speaker: |
James Hegg
National Director of Training
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| Speaker Bio: |
As National Director of Training for NuCo Corporation, James brings over 20 years of technical product & project management experience to the team. James' responsibilities include development of NuCo's training programs & managing the web presence team.
Prior to joining NuCo in 2009, James was Director of Technical Product Solutions at FMG, head of Global Logistics at GE Security and Western Area Manager for SubMicron Systems. His background includes semiconductor manufacturing, aviation security and six-sigma quality processes. James has supported customers in the semiconductor industry including AMD, TI, Phillips, LSI Logic, National, IDT & VLSI.
James graduated from DeVry University in Chicago with a BSEE in 1988. James relocated from Chicago to Silicon Valley in 1990 where he now resides.
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| Date: |
March 25, 2010 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
2010 Semiconductor Industry & Economic Conditions
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| Description: |
In 2010, the semiconductor industry is headed for growth, after 2 years of consecutive decline in 2008 and 2009 during the global economic downturn. As the global economy recovers, we examine the factors affecting semiconductor growth and the possible outcomes, especially:
economic factors
capacity & capital spending
inventory
electronics
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| Speaker: |
Shelly Van Dyke
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| Speaker Bio: |
Shelly Van Dyke is in Corporate Strategy at Freescale Semiconductor, Inc., where she provides strategic,
market & economic analysis, working with contributors from across Freescale businesses and throughout the industry.
She has more than 22 years experience in the semiconductor industry, including positions in business and manufacturing
strategy, technology licensing, multiple process and device engineering and management positions in wafer fabrication,
and quality. Shelly has a Bachelor of Science degree in Chemical Engineering from The University of Texas, and an MBA
from Regis University.
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| Presentation: |
Available |
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| Date: |
April 22, 2010 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Substrate Engineering for Performance, Power Saving and Scalability Advantages
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| Description: |
In the past 40 years, steady scaling transistor dimension and supply voltage for each new generation of
CMOS technology by a factor of 0.7x smaller than those of the previous generation enables continuous
improvements of integrated-circuit performance, power, density or cost/function, as demanded by mobile
communication. However, transistor and power supply scaling has slowed down recently due to fundamental limits
leading to increasing in power density, variability and process/design complexity. The classical scaling is no
longer possible to follow Moore’s law without innovation in materials, process, tool and device architecture. A
transition to engineered substrate technology is essential, as exemplified by SOI and its more advanced adaptations.
The advances in engineered substrates and some key applications are described.
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| Speaker: |
Bich-Yen Nguyen
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| Speaker Bio: |
Bich-Yen Nguyen recently join Soitec as a Senior Fellow representing Soitec’s R&D and supporting the development
of new fields and applications for Soitec’s core technologies. Bich-Yen is also responsible for the Soitec USA R&D
projects. Prior to joining Soitec, Bich-Yen was a senior manager at Freescale Semiconductor and a Motorola Dan Noble Fellow.
Bich-Yen has been recognized for her leadership and research in developing Freescale/Motorola's CMOS technology for
advanced integrated circuit products. She also was instrumental in transferring process technology to production since
1980, which resulted in a competitive market entry position for Freescale/Motorola. Her honors and awards include recipient o
f Distinguished Innovation award in 1991, Motorola Science Advisory Board Associate in 1992, Dan Noble Fellow in 2001, Master
of Innovation Award in 2003. In 2004, she received the 1st National Award “Women in Technology Lifetime Achievement Award”.
She holds over 100 worldwide patents and has authored more than 150 technical papers on IC process, integration and device
technologies. She gave several invited talks, panel discussion and keynote speaker at the major international conference
and university. She also served as a committee member for IEDM conferences and currently serves as a technical committee member
of the ICICDT, ECS, SOI and ESSDERS
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| Date: |
May 27, 2010 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
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| Topic: |
3D Interconnect Challenges and How Matching Networks Provide A Path For Performance Improvement
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| Description: |
As MEMS technology has improved with advancements in micro-fluidics, gyroscopes, and various sensors so has industries
capability to interconnecting these devices. 3D interconnect is not a new idea; however 3D interconnect is only recently
an idea that is being realized within our industry. We now see the development of multi stacked chips integrating CMOS
with analogue RF with MEMS. Finally with the enablement of die to wafer bonding we are seeing an exponential curve in industry
flexibility and potential growth. With this tremendous growth comes tremendous challenges as to how these systems are integrated
maintaining a high signal to noise ratio, and optimal energy transfer. This talk is the first of three regarding this issue,
highlighting where we are currently as an industry, some of the challenges we have faced and how we have overcome those challenges,
and finally the benefits that can be realized by incorporating various matching network approaches within the interconnect of these
new novel device systems.
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| Speaker: |
Jeffrey Visser
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| Speaker Bio: |
Jeffrey Visser is the Integration and Test Manager at SVTC Technologies, Inc. SVTC is a development solutions provider to a broad
range of technologies from CMOS, Bio-MEMS, Photo-voltaic, MEMS, III-V to 3D interconnect and NVM. He has ~20 years experience in
industry, with 13+ in semiconductors and has lead or worked on projects and technologies ranging from MRAM, JFET integration, NVM
development, BEOL integration, CMP development, yield/ cycle-time improvement, to RF/microwave design and VLSI layout. Jeffrey has
been working on his Ph.D. in Electrical Engineering from Clarkson University since 2006, has an MSEE from California Polytechnic
University Pomona, and a BSEM from Southern Illinois University Carbondale.
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| Date: |
July 29, 2010 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Rio Grande Conference room at SVTC
(view map)
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| Topic: |
Flexible Thermoelectric Energy Generation
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| Description: |
The development of efficient thermoelectric materials could have a dramatic impact on the energy problems facing 21st century society.
Thermoelectric materials on flexible substrates offer unique opportunities for scavenging energy through incorporation in building materials,
for example window glass, or photovoltaic systems designed to scavenge photon energy across the entire spectrum of solar radiation.
To develop such materials, significant improvements in the efficiency of thermoelectric materials is required. Moreover, the
development of flexible thermoelectric materials for energy generation places an additional constraint on what has historically
been a very difficult materials problem. Here, we discuss opportunities to utilize the scattering of phonons at interfaces to
disordered solids for generating such materials. In particular, we have utilized phonon wavepacket molecular dynamics simulations
to examine the transport of energy through thermoelectric nanostructures. The results indicate that opportunities exist to independently
optimize the electronic structure of the thermoelectric nanostructure from that of its lattice vibrations.
|
| Speaker: |
Bruce White
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| Slides: |
Speaker's Slides |
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| Date: |
August 26, 2010 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Rio Grande Conference room at SVTC
(view map)
|
| Topic: |
The "Bosch" Process for Deep Silicon Etching
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| Description: |
The so-called "Bosch" process is the etch process of choice whenever a
device requires etching deep into a silicon substrate, for example to
make MEMS devices or through wafer vias. The Bosch process, also called
"Time-Multiplexed Deep-Etching" (TMDE) is often called upon to produce
deep trenches and/or vias at high rates. While this process has been
both modeled and experimentally studied by a wide variety of
researchers, it is highly complex and significant issues remain. Aspect
ratio dependencies, selectivity and the ability to use photoresist masks
(instead of SiO2) are all examples. In this talk I will provide a
primer on the Bosch process, make some comparisons to competing
processes (such as cryogenic etching) and describe some recent research
at the University of Texas at Dallas into TMDE. For example, looking at
the deposition step in isolation clearly shows an ion-enhanced aspect
that few models and studies have previously recognized. It may prove
important.
|
| Speaker: |
Dr. Larry Overzet
UT Dallas
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| Speaker Bio: |
Lawrence Overzet received his Ph.D. (under the direction of Prof. J.
Verdeyen) in Electrical Engineering from the University of Illinois at
Urbana-Champaign in 1988. He became an Assistant Professor at UTD in
late 1988. At that point, the electrical engineering program was just 2
years old. He was promoted to the position of Professor of Electrical
Engineering in 2000 and became the associate department chair in
electrical engineering in 2006. (The UTD EE dept now has ~45 faculty.)
He has over 60 publications and about 170 presentations at international
symposia (>40 invited). He is a long time member of the American Vacuum
Society, senior member of the IEEE, is a Registered Professional
Engineer, an Honorary Member in the Golden Key International Honour
Society and was UTD's Polykarp Kusch Lecturer for 2005 (the highest
honor annually bestowed upon a UTD faculty
member.) His research interests are varied but have primarily revolved
around the study of plasmas used in semiconductor processing.
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| Date: |
September 17, 2010 |
| Time: |
5:30pm - 7:00 pm Seminar |
| Location: |
Rio Grande Conference room at SVTC
(view map)
|
| Topic: |
TBA
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| Description: |
TBA
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| Speaker: |
Prof. Santosh Kurinec (Rochester Institute of Technology)
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| Date: |
October 28, 2010 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Rio Grande Conference room at SVTC
(view map)
|
| Topic: |
Engineering Ethics and Practice
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| Description: |
This presentation will update you on recent changes to professional engineering laws and rules,
important issues related to engineering practice and ethics, and other
issues related to being a Professional Engineer in Texas.
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| Speaker: |
Lance Kinney
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Thuy Dao