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Abstract: Clock frequencies of the high-speed integrated circuits, packages, and systems have increased over the GHz frequency range.  The density of transistors per square millimeter greatly increased. More and more circuit modules designed for different purpose share the same piece of silicon in one package, such as the system-on-chip (SOC) and system-on-package (SIP). At the same time, the working frequency becomes higher and higher. The electromagnetic compatibility (EMC) and signal integrity become a very important issue in high speed electronic design. The potential EMC problems should be found and solved as early as possible to reduce the cost on the design-manufacture-test cycle.  This talk will introduce the fundamental EMC and signal integrity issues in high-frequency electronic circuits and its packaging. The key EMC problems arising from the high-speed IC& package will be discussed.  The current modeling and simulation methods used for IC& package EMC problems will be presented.

Abstract: With the trend of fast edge rates, high operation frequencies, and low voltage in high-speed or high-frequency circuits, power/ground noise caused by simultaneously switching currents has become one of the major concerns for high-speed or mixed-signal circuit designs. In this talk, the fundamental concept for the power integrity (PI) design is first introduced, including the power distribution network (PDN) and its impedance, the mechanism of the power noise, and the design issues caused by the power noise. Several commercial solutions to suppress the noise, such as SMT capacitors, embedded capacitor, and on-chip capacitors, will be presented. Recently, electromagnetic band gap (EBG) structures are proposed to be an alternative approach for power noise suppression. Several novel electromagnetic bandgap (EBG) structures with efficient noise suppression capability will also be demonstrated in this talk.

Abstract: Driven by the impressive growth of the communication industry we see a rapid convergence of digital computing and analog wireless technology.  This has become possible due to the progress of, semiconductor technology into the nanometer regime which is going to continue for the next  ten to fifteen years.  High-level integration with unprecedented functionality has been achieved through 3D packaging techniques known as system-on-chip (SOC) or system-in-package (SIP) designs.  Key aspects of this technology are stacked substrates to form a multilayered package which provides an additional degree of freedom in the package design on the one hand. On the other hand, vertical integration has introduced a new degree of design complexity. Traditionally, signal and power distribution networks (SDN and PDN) have been analyzed separately because they were located far away from each other on a 2D PCB. This is no longer possible since in today’s 3D packages the layers containing SDN and PDN are in close proximity. Global coupling effects such as simultaneous switching noise (SSN) demand a modeling methodology on the system level requiring co-simulation of signal and power integrity.  Therefore, new modeling approaches are in high demand to solve the challenges imposed by the complexity of nano-scale silicon chips and the necessary packaging. This presentation will overview the advancements of computational electromagnetics with applications in complex electronics package integration and   to address the challenges in system-level signal and power integrity and electromagnetic interference analysis.

Abstract: Signal integrity simulation and modeling is becoming more and more important for high-speed chip, package, or PCB designer in the trend of SoC and SiP. In this talk, a case study about a TFT driver board for establishing a SI simulation in SPICE environment is first presented. The importance of the SPICE-based model for the discontinuities (or transitions), such as via, bends, BGA balls, etc., in signal path will be highlighted. A general time-domain approach for synthesizing the equivalent macro-models for those discontinuities will be finally proposed.

Reproducibility of Radiated Emissions Test Data

Location: Front Range Community College, Room L107 (see map), 3645 W. 112th Ave., Westminster, CO. Directions maybe found at:
  http://www.frontrange.edu/FRCCTemplates/FRCC7.aspx?id=109.

Room Location Map (pdf)

Time: 6:30 p.m. social, 7:00 p.m. presentation.

Abstract:  Necessity was the mother of site-to-site reproducibility evaluation for radiated emissions testing.  In the 1980's, H-P had products that were being cooperatively developed and tested in Colorado and California.  When the inevitable happened, and two test facilities gave conflicting test results, we were forced to figure out whether the differences were due to the test facilities or other causes.  This led to a reproducibility program that is going strong today, with 30+ participating sites, H-P and non-H-P, around the world.  This presentation will discuss what we learned about radiated and conducted emissions reproducibility, and how we got where we are.

Biography:  Lowell Kolb holds BS and MS degrees in Electrical Engineering from South Dakota School of Mines and Technology, 1974 and 1975, respectively.  He has been employed by Hewlett-Packard company in Loveland and then Fort Collins, Colorado, continuously since January of 1975, with various positions in research and development, quality assurance, and manufacturing, starting with desktop computers, which evolved into workstations.  He has been focusing almost exclusively on electromagnetic compatibility for the past 20 years, and is currently an EMC engineer in the hardware test center.  Lowell holds seven patents, all of which are EMC-related.

Please send your RSVP for both the pizza social and the chapter meeting to Chuck Still (Sun Microsystems, electronstill@comcast.net).

Civilian & Military Standards Testing: What's in Common, What's Different and What Testing Should be Done to Make the Best Products?

Location: Front Range Community College, Room L107 (see map), 3645 W. 112th Ave., Westminster, CO. Directions maybe found at:
  http://www.frontrange.edu/FRCCTemplates/FRCC7.aspx?id=109.

Room Location Map (pdf)

Time: 6:30 p.m. social, 7:00 p.m. presentation.

Abstract:  Mr. Greb will present a comparison between commercial EMC test requirements and MIL-STD requirements.  His comparison will include test levels and test methods, highlighting the differences between the two environments.  In particular, his presentation will focus on the differences between EN 55022/24 and MIL-STD-461E requirements.  He will touch on some of the design implications associated with the different test environments and will also highlight some of the new requirements of MIL-STD-461F.

Please send your RSVP for both the pizza social and the chapter meeting to Chuck Still (Sun Microsystems, electronstill@comcast.net).

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