RMCEMC October 30, 2007

Download the presentation here

Multi-Gbps channel analysis for the IC and system level designer

Ian Dodd
Agilent Technologies

Tuesday, October 30th, 2007

Location: Front Range Community College, Timberline Room S118 (see map), room L-107, 3645 W. 112th Ave., Westminster, CO. Directions maybe found at:
  http://www.frontrange.edu/FRCCTemplates/FRCC7.aspx?id=109.

Room Location Map (pdf)

Time: 6:30 p.m. pizza & cinnamon stick social (sponsored by Agilent), 7:00 p.m. meeting starts.

Multi-Gbps Channel Analysis for the IC and System Designer - Self clocked multi-Gbps serial channels are now a standard feature in computing and communications systems. The existing generation of channels operates on standard PCB substrate at up to 3Gbps per conductor pair. New designs are being deployed that will operate on standard PCB substrate at 6-10 Gbps per conductor pair.

The design and testing of the drivers and receivers for multi-Gbps serial channels is becoming increasing sophisticated. The designers of these silicon modules must employ advanced proprietary signal processing techniques to obtain low bit error rates despite the highly lossy and dispersive medium. Once a design is complete they must create comprehensive documentation and models while protecting their intellectual property.

The PCB system designer is also faced with new challenges in the simulation, realization and testing of these multi-Gbps channels. These include obtaining accurate models for the drivers and receivers they have selected and evaluating signals exhibiting a closed eye at the receiver input pin.

Bio: Ian Dodd graduated with a BSc (with honours) in  Physics from  Loughborough University, England and a MSc, in Technological Economics, Stirling University, Scotland.

He has over 20 years of experience in leading the development and marketing of advanced electronic design automation tools. He was an early evangelist of specialized EDA tools for signal integrity analysis and has the unique distinction of having experienced all facets of signal integrity tool design, development, marketing and support. He was the architect of three generations of signal integrity tool suites marketed by Intergraph Electronics, VeriBest Inc. and Mentor Graphics Inc.

Ian has been an active contributor to the IEEE and industry working groups including IBIS and CFI. He has presented many papers on signal integrity and other EDA related subjects. He is currently a signal integrity business development consultant working with the EEsof division of Agilent Technologies, Inc.

 

PICTURES