Navigation Menu Script

Page optimized for IE 6/7/8.

IEEE Home | Shop IEEE | Join IEEE | myIEEE | Contact IEEE | IEEEXplore

 WMED-Logo

IEEE Workshop on Microelectronics and Electron Devices (WMED)

 

Boise

 

 

WMED 2011 Technical Program

 

Friday, April 22nd, 2011 8:00AM-6:00PM

 

8:00 AM

Check In and Door Registration

With Continental Breakfast

8:30 AM

Welcome to WMED 2011

Room: Simplot BD

8:45 AM

Keynote Address: “Atoms to go…..Ionic Memory and Data Storage”

Prof. Michael N. Kozicki, Adesto Technologies

Room: Simplot BD

9:45 AM

Break and Poster Setup

10:00 AM

Invited Tutorials (Parallel sessions)

Tutorial 1: “Advanced CMOS Transistor Technology: Past, Present and Future”

Prof. Suman Datta, Penn. State

Room: Simplot BD

 

Tutorial 2: “Energy Efficient Multi-Gb/s I/O: Circuit and System Design Techniques”

Bryan Casper, Intel Circuit Research Labs

Room: Simplot C

NOON

Buffet Luncheon

Provided by WMED

Room: Hatch

1:00 PM

Invited Talk: “Promises and Challenges in Light-Emitting Diodes for Lighting Applications”

Prof. E. Fred Schubert, RPI

Room: Simplot BD

2:00 PM

Invited Talk: “Label-Free Biosensing with Silicon Nanowires”

Prof. Mark A. Reed, Yale University

Room: Simplot BD

3:00 PM

Break

3:15 PM

Contributed Papers (Parallel Sessions)

Session 1 Process and Device

Room: Simplot BD

 

Session 2 Solid State Circuits

Room: Simplot C

5:30 PM

Poster Presentation and Refreshments

Room: Hatch

 

Contributed Papers

Session 1

Room: Simplot BD

3:15 PM

“Structural Study of Ag-Ge-S Solid Electrolyte Glass System for Resistive Radiation Sensing”

P. Chen, M. Ailavajhala, M. Mitkova, D. Tenne, Boise State University; I. Sanchez Esqueda, H. Barnaby, Arizona State University

3:35 PM

“Friction Based Endpoint Technique for Barrier Polish During CuCMP”

S. Zhu, J. Hofmann, A. Jindal, Micron Technology, Inc.

3:55 PM

“Finite Element Modeling of a Back Grinding Process for Through Silicon Vias”

A. H. Abdelnaby, G. P. Potirniche, F. Barlow, A. Elshabini, University of Idaho; R. Parker, Micron Technology, Inc.

4:15 PM

“VT statistics on nanoscale NAND Flash arrays”

A. Spessot, A. Calderoni and P. Fantini, Micron Technology, Inc.

4:35 PM

“High-Performance Transistor Evaluation for Low-Cost Embedded DRAM”

H. Furusawa, S. Nogami, T. Ogawa, M. Kumazaki, N. Okada and H. Yamamoto, Micron Technology, Inc.

Session 2

Room: Simplot C

3:15 PM

“Self-Calibrating Continuous-Time Equalization with Multiple Degrees of Freedom”

T. M.. Hollis, Micron Technology, Inc.

3:35 PM

“Adjustable supply voltages and refresh cycle for process variations and temperature changing adaptation in DRAM to minimize power consumption”

L. Tran, F. J. Kurdahi, and A. M. Eltawil, University of California Irvine.

3:55 PM

“All digital duty-cycle correction circuit design and its applications in high-performance DRAM”

F. Lin, Micron Technology, Inc

4:15 PM

“A Non-Volatile Memory Array Based on Nano-Ionic Conductive Bridge Memristors”

S. Wald, J. Baker, M. Mitkova, N. Rafla, Boise State University

Poster Session and Refreshments

Room: Hatch

Time: 5:00 PM

“Optimized Germanium Co-Implant with B2H6 PLAD for Better Advanced PMOS Device Performance”

J. L. Liu, S. Qin, J. Hu, A. Mcteer, Micron Technology, Inc

“Design of low noise CMOS charge pump with adjustable output voltage and adjustable power”

S. A. Stickel, Boise State University

“Measurement and Simulation of Various Geometries of LTCC Electron Hop Funnels”

T. Rowe, J. Browning, Boise State University

“Efficient Design and Synthesis of Decimation”

R. M. R. Koppula, S. Balagopal, V. Saxena, Boise State University

“A Novel Material Solution for Non Volatile Contact Bridge Memristive Memory Fabrication”

M. R. Latif , E. Coleman, M. Mtikova, P. Chen, Boise State University, and G.S. Tompa, Structured Materials Industries, Inc Piscataway, NJ USA

“Radiation induced effects in pure and Ag doped Ge-Se films”

M. S. Ailavajhala, P. Chen, M. Mitkova, Boise State University, and H. Barnaby, Arizona State University

“Design Techniques for a 70 Gbps CMOS Multiplexer”

P. Osheroff, G. S. La Rue, Washington State University

 

 

Workshop Sponsors

 

 

 

Boise Section

 

 

 

Boise Chapter

 

 

 

 

 

 

 

This workshop is receiving technical co-sponsorship support from the IEEE Electron Devices Society.

 

Copyright 2008 IEEE All Rights Reserved.

Use of this website signifies your agreement to the Terms of Use.

For questions or comments, please contact the WMED Webmaster.