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A Multi-Synchronous UART Design

D. Bhadra, V. S. Vij, and K. S. Stevens
University of Utah
Salt Lake City, UT, USA


Universal Asynchronous Receiver Transmitter (UART) implements serial communication between peripherals and remote embedded systems at high reliability and consists of two frequency domains. The multi-frequency nature of this peripheral favors its implementation using a multi-synchronous design methodology based on Relative Timing (RT). A full duplex UART which uses a novel multi-synchronous architecture is presented. This multi-synchronous design enables elasticity in the peripheral leading to power and energy benefits. Synchronous and multi-synchronous versions for the UART design were implemented and compared to illustrate the benefits of multi-synchronous design in terms of area, power, and energy. The synchronous UART consumed 4? the power of the multi-synchronous design at nearly the same area.





This workshop is receiving technical co-sponsorship support from the IEEE Electron Devices Society.

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