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IEEE Workshop on Microelectronics and Electron Devices (WMED)

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Flash Memory Scaling: Challenges and Opportunities (Invited)

R. Koval, Intel Corporation
Boise, ID, USA


In the past decade, we've witnessed the powerful force of cost reduction enabled by >100x increase in NAND flash memory density, which allowed NAND flash to surpass NOR flash in bits shipped and, most recently, total flash memory revenue to surpass DRAM revenue. Aggressive technology scaling and advances in error management facilitate the scaling of NAND flash down to ~10nm half pitch and >100Gb densities, empowering NAND flash to maintain its current position as technology driver in the semiconductor industry. The rapid pace of innovation continues to raise the bar and delay the introduction of so-called emerging memories. Beyond the ~1Xnm node, several fundamental scaling challenges associated with the flash cell invented nearly half a century ago require a paradigm shift to sustain Moore's law into the next decade. Vertical NAND flash offers several important advantages that enable continued cost/bit scaling but also poses a new set of scaling challenges. Addressing those challenges will widen the cost/bit lead over competing technologies and allow NAND flash to scale to the Terabit era and retain its position as the incumbent technology for the foreseeable future.

Speakerís biography:

Randy Koval received the B.S., M.S., and Ph.D. degrees in Electrical Engineering at the Pennsylvania State University and joined Intel in 2002. He has contributed to several generations of NOR and NAND MLC flash technology development during the past ten years at Intel. He is currently with the Nonvolatile Memory Solutions Group at Intel and part of a joint development project with Micron Technology that was established to develop next generation memories. His research interests include flash cell device scaling and reliability physics. He has authored or co-authored over 40 refereed journal publications, peer-reviewed conference and technical digest papers and is a senior member of the IEEE.





This workshop is receiving technical co-sponsorship support from the IEEE Electron Devices Society.

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