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Invited Tutorial - Computing Beyond the 11nm Node: Which Devices will we Use?

Dr. Wilfried Haensch, IBM T. J. Watson Research Center

Abstract:

The enormous success of Si CMOS technology is based on the economy of scale. Cost is driven down by increasing wafer size and decreasing feature sizes while performance is steadily growing. The pervasive nature of microelectronic can be seen in all aspects of daily life. The industry enjoyed the success story for several decades by simply following the scaling laws. More recently it is realized that increased performance will come at an unacceptable cost of power and conventional CMOS scaling is rapidly coming to an end. The quest for solutions is in full swing how to meet the computational demands for the foreseeable future. Possible solutions are the change of device architecture and the introduction of high mobility materials for the devices to boost performance. Beyond the classical device materials Si, Ge, and some III/V compounds carbon in the form of carbon nano tubes or graphene are suggested as possible alternative candidates for digital applications. Replacing the field effect transistor by a tunnel FET holds the promise of a low power switch that can be realized with conventional channel materials. Moving from electrical charge to other state variables, like for instance spin, might provide new possibilities to meet the computational needs in the future.

Speaker’s biography:

Wilfried Haensch received his Ph.D. in 1981 from the Technical University of Berlin, Germany in the field of theoretical solid state physics. He started his career in Si technology 1984 at SIEMENS corporate research Munich. There he worked on high field transport in MOSFETs. In 1990 he joined the DRAM alliance between IBM and SIEMENS to develop quarter micron 64M DRAM . From there he moved in 1996 to INFINEON’s manufacturing facility in Richmond VA to be involved in the production of various generations of DRAM. In 2001 he joint IBM TJ Watson Research Center to lead a group for novel devices and applications. In this function he was responsible for the exploration of device concepts for 15nm node and beyond, new scaling concepts for memory and logic circuits, including 3D integration. He is currently responsible for post CMOS device solution and Si technology extensions. This includes carbon electronics for RF and digital applications and optical and electrical material properties of graphene and carbon nano tubes. He is the author of a text book on transport physics and author/co-author of more than 100 publications. He was awarded the Otto Hahn Medal for outstanding Research in 1983. He was named IEEE Fellow in 2012.

This workshop is receiving technical co-sponsorship support from the IEEE Electron Devices Society.

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