December 4, 2001 - The Design of Flash Memory
    Speaker: John Y. Hsu   Cal Poly Computer Engrg Dept

>Abstract
General topics include the design principles of bipolar and unipolar transistors, doped silicon, drain, source, and the aluminum-based metal gate for control. Special topics include the floating gate, word line, bit line, and source line of a transistor cell that is non-volatile.
What is the key difference among a read, write, erase, and program operation in MOS memory
design? Finally, how can we store two bits or three bits per each transistor cell? What are the applications?

>About the speaker
John Y. Hsu received his B.S.E.E from National Taiwan University (1955-59); his M.S.E.E. (1963-64) and Ph.D. (1967-69) from the University of California, Berkeley specializing in computer system hardware and software. He is currently a professor of computer engineering at California Polytechnic State University in San Luis Obispo. In 1976, he was a ACM national lecturer. In 1979, he was a visiting research professor at National Taiwan University. He held many industrial job titles, such as computer architect, project engineer, and senior software specialist. In addition, he has done over 10,000 hours of consulting work for companies including Federal Electric/ITT, ILLIAC IV, III in Taiwan, CDC, IBM, etc. Dr. Hsu is a member of IEEE and ACM.
 
 

The Design of Flash Memory

               John Y. Hsu
               Cal Poly State University,
               San Luis Obispo, CA 93407
               jyhsu@calpoly.edu
               http://www.csc.calpoly.edu/~jyhsu



 
 
 
 

History of Transistors


o  At Bell lab three scientists, John Bardeen, Walter Brattain, and William Shockley invented the bipolar junction transistor in 1947.

o  What is a transistor?
A transistor is a current amplifier made of semiconductor, aka solid-state material, e.g. Si (Silicon), Ge (Germanium), and GaAs (Gallium Arsenide).

o  Among all the semiconductor materials, Si is the most popular one for it is reliable, fast, and cheap.
 

Doped Silicon

o  A N-layer is a piece of silicon that is doped with extra electrons so the material carries free negative charges.  By adding P (Phosphorous) to Si, we obtain N-type silicon (N-Si).

o  A P-layer is a piece of silicon that is doped with extra holes so the material carries free positive charges.  By adding B (Boron) to Si, we obtain P-type silicon (P-Si).

o  Both N-layer and P-layer are electrically neutral.
 

Original Idea


o  The original idea was to employ the Unipolar transistor concept.

o  One piece of N-type silicon was clamped by two metal parts at the two ends.  One end is known as the drain and the other end is known as the source.  The middle is attached to a metal wire.  By applying a positive voltage to the middle wire, negative charges (i.e. electrons) would flow from the source to the drain, or the current would flow from the drain to the source.

o  This great idea would not work without refinements.
 

Bipolar Junction Transistors

o  There are two types of bipolar junction transistors: NPN and PNP.  Each type has three layers with two junctions.

o  In a NPN bipolar junction transistor, the two ends are N-layers and the middle is a thin P-layer.  The middle layer is known as the base whose purpose is to control current flow.  The top layer is called the collector and the bottom layer is the emitter.  In regard to the size of doped area, the collector is bigger than the emitter in a junction transistor.  {Figure 1}

o  The base-emitter (P-N) junction acts like a diode.  If the diode is forward biased, an amplified current flows from the collector to the emitter.
 

Unipolar Transistors

o  There are two types of unipolar transistors.  Precisely, they are Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and both types were derived from the original idea.

o  Each MOSFET uses a doped channel that may be positively or negatively doped.  The doped channel has two ends (i.e. regions) that are doped oppositely.  On top of the doped channel, a thin layer of Silicon Oxide (Si O2) is deposited.  On top of the Silicon Oxide layer, there is a metal gate.

o  A NMOS (N-channel MOS) transistor has a channel, i.e. one piece of silicon substrate that is positively doped (P-Si).  {Figure 2}

o  The two ends are known as the D (Drain) region and the S (Source) region, respectively.  The two regions are negatively doped (N-Si) with equal physical sizes.

o  Above the channel and regions, there is a Silicon Oxide layer deposited as dielectric in a capacitor.  Above the Silicon Oxide, there is an aluminum-based metal gate for voltage control.

o  When a positive voltage is applied to the metal gate, free negative charges are induced in the channel so current flows from the drain to the source, i.e. the NMOS transistor is turned on.
 

Flash Memory Design

o  Flash memory was developed at Intel in 1988.  Amazingly, it is both programmable and non-volatile.

o  Flash memory has no moving parts and it can be electrically read, erased, and programmed in the host system without being taken out.

o  A flash memory has address lines, data lines, and control lines.  {Figure 3}

o  The address lines are uni-directional to the memory as input.

o  The data lines are bi-directional for input and output.

o  The control lines specify a command code for read, erase, or program.

o  A read operation produces an output on the bit line.

o  An erase operation can change bits to 1s.

o  A program operation can change bits to 0s.

o  In order to write a block of bits, issue an erase operation then a program operation.
 

Floating Gate

o  A flash memory cell is a modified NMOS transistor with a floating gate.

o  On top of the channel, a thin layer of oxide is deposited as the tunnel.

o  A layer of poly-silicon is deposited on top of the oxide as the floating gate.

o  Another layer of oxide is deposited on top of the floating gate.

o  The front aluminum-based gate is deposited on top for voltage control.

o  The raw states of a flash memory are 1's because each floating gate carries no negative charges.

o  Because the floating gate is insulated by oxide, any negative charge on a floating gate does not leak, even if the power is turned off.
 

Theory of Operations

o  WL (Word Line) is the horizontal line and BL (Bit Line) is the vertical line.  The modified NMOS at the intersection has its front gate connected to WL (i.e. the decoded address), a drain connected to BL, and a source connected to SL (Source Line).  The BLs are negative OR-tied (i.e. NOR cell design), and the SLs are connected to a common ground.

o  The voltage combinations applied to WL and BL define an operation: read, erase, or program.

o  During a program operation, a high voltage is applied to the front gate via the WL.  If a high voltage is applied to the drain via the BL, a bit 0 is to be programmed.  Through tunneling effect, the excited electrons pushes through the thin oxide layer.  Alas, they are trapped on the floating gate, so the gate carries a negative charge.  If the floating gate carries negative charges over a threshold, the bit stored in the cell is 0.  If a low voltage is applied to the drain via the BL, the amount of electrons on the floating gate do not change much so its state remains the same.

o  During an erase operation, a higher voltage is applied to the front gate by the WL and the drain is left open.  As a result, the excess electrons flow from the floating gate to the SL, then to the ground so the floating gate becomes neutral again.

o  During a read operation, a high voltage is applied to the front gate by the WL.  If the selected transistor is turned on, its drain output is pulled low on the BL defined as 1 using negative logic.  This is coined as the NOR cell design.  If the selected transistor is not turned on, its drain voltage is high on the BL defined as 0.
 

Two-bit Per Cell Design

o  The negative charge on a floating gate is very much like a barrier, or negative bias, to the input.  The amount of negative charges on the floating gate defines the state of the bit cell.

o  If we intend to store one bit per cell, then a floating gate with no negative charge is defined as 1.  Thus, a nominal high voltage applied to the front gate will turn on the transistor.  A floating gate with negative charge is defined as 0 for a nominal high input will not be able to turn on the transistor.

o  Advanced technology allows two bits to be stored in one modified NMOS transistor.  This is the two-bit per cell design as implemented in Intel StrataFlash.  In such a design, the amount of negative charge on a floating gate has four levels.

o  Each level represents an input voltage to turn on the transistor.  Henceforth, each input level represents the encoding of two bits.  The access time may be longer, but the capacity is doubled.

o  If the amount of negative charge on a floating gate has eight levels, then 3 bits of information can be stored per cell.

o  Commercial flash memory is available in the form of a card, or a stick.  A flash memory card has a dimension of 45 by 37 by .76 mm (millimeter) and it can store 256 MB and support dual voltages of 3.3 v. or 5 volts.  A flash memory can sustain heavy usage without data loss.