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Upcoming Events:

September 21, 2009 Event Cosponsored by the IEEE SCV Communications Society:

6:30pm: Networking/Pizza Social
7:00pm: Announcement
7:05pm: Presentation
8:15pm: Adjourn
Cost: Free. $2 donation accepted for food.

Location: National Semiconductor, Building E Auditorium

Title

Low-Voltage Oversampling Analog-to-Digital Conversion

Speaker

Dr. Bruce A. Wooley (Robert L. and Audrey S. Hancock Professor of Engineering, Dept. of E.E., Stanford University)

Abstract

Through the exchange of resolution in time for that in amplitude, oversampling methods are now widely used to enable the realization of high-resolution analog-to-digital converters in scaled CMOS VLSI technologies. So-called oversampling modulators combine coarse quantization at sampling rates well above the Nyquist rate with feedback and subsequent digital signal processing to avoid the need for precision analog circuits. Such modulators were originally conceived in the mid-twentieth century in the form of delta modulators, which digitize the rate of change of a signal, rather than the signal itself. However, noise-shaping modulators that directly encode the signal proved to be a more robust approach and have subsequently come into widespread use. In particular, cascades of inherently stable sigma-delta (or, equivalently, delta-sigma) modulators are an efficient means of extending the dynamic range of oversampling converters that are largely immune to both analog circuit imperfections and fundamental stability concerns. This presentation begins with an overview both architectural and circuit issues associated with the design of noise-shaping modulators, and then presents examples of some approaches to their implementation under increasingly severe constraints on power dissipation and supply voltage.

Biography

Bruce A. Wooley is the Robert L. and Audrey S. Hancock Professor of Engineering at Stanford University. He received the B.S., M.S. and Ph.D. degrees in Electrical Engineering from the University of California, Berkeley in 1966, 1968 and 1970, respectively. From 1970 to 1984 he was a member of the research staff at Bell Laboratories in Holmdel, NJ, and he joined the faculty at Stanford in 1984. At Stanford he has served as the Chair of the Department of Electrical Engineering, the Senior Associate Dean of Engineering and the Director of the Integrated Circuits Laboratory. His research is in the field of integrated circuit design, where his interests include low-power mixed-signal circuit design, oversampling A/D and D/A conversion, circuit design techniques for video and image data acquisition, high-speed embedded memory, noise in mixed-signal integrated circuits, and circuits for wireless and wireline communications.
Prof. Wooley is a Fellow of the IEEE and a past President of the IEEE Solid-State Circuits Society. He has served as the Editor of the IEEE Journal of Solid-State Circuits and as the Chairman of both the International Solid-State Circuits Conference (ISSCC) and the Symposium on VLSI Circuits. Among the awards he has received are the University Medal from the University of California, Berkeley, the IEEE Journal of Solid-State Circuits Best Paper Award, recognition for his Outstanding Contributions to the Technical Papers of the International Solid-State Circuits Conference, the IEEE Third Millennium Medal, the Outstanding Alumnus Award from the EECS Department at the University of California, Berkeley, and the IEEE Solid-State Circuits Technical Field Award.

October 8, 2009 Event:

6:30pm: Networking/Pizza Social
7:00pm: Announcement
7:05pm: Presentation
8:15pm: Adjourn
Cost: Free. $2 donation accepted for food.

Location: Cadence Design Systems, Building 5

Title

Reverse Engineering in the Semiconductor Industry

Speaker

Mr. Randy Torrance, B.A.Sc.E.E.,M.A.Sc.E.E. (Chipworks)

Abstract

The continuous drive of Moore's law to increase the integration level of silicon chips has presented major challenges to the reverse engineer, obsolescing simple teardowns and demanding the adoption of new and more sophisticated technology to analyze chips. The following types of analysis will be covered in detail:

This presentation is an update of the invited paper given at the 2007 IEEE Custom Integrated Circuits Conference (CICC) with more focus on circuit extraction and cross-referencing between circuit schematics and the 1000's of physical layout images obtained through generating a mosaic of scanning electron microscopy across all device layers.

Biography

Randy Torrance leads the Circuit Analysis team for the Technical Intelligence group at Chipworks. During Randy's 22 years in the technology industry he has held senior technical and management positions in the IC design and electronic systems areas.

Prior to joining Chipworks Randy was Director of IC Technology Development for Atmos/Mosys, and was responsible for teams designing cutting-edge embedded memory macros. Before that he spent 12 years at Mosaid, where he held positions ranging from Senior Design Engineer through Manager IC Design to Director of IC Design, Switching Products. Here he led groups designing commodity and custom memories, and large ASICs for the graphics and networking markets.

Randy holds a B.A.Sc. and M.A.Sc. in Electrical Engineering from the University of Waterloo.

October 19, 2009 Event: IEEE CAS Distinguished Lecturer

6:30pm: Networking/Pizza Social
7:00pm: Announcement
7:05pm: Presentation
8:15pm: Adjourn
Cost: Free. $2 donation accepted for food.

Location: Cadence Design Systems, Building 5

Title

Energy-efficient on-chip power management: System, circuit and device perspectives

Speaker

Dr. Eduard Alarcón (Professor, Universitat Politecnica De Catalunya)

Abstract

Trends in portable applications such as mobile terminals for next generation communications proceed in the direction of increasing the computational load while concurrently reducing size and enhancing operating lifetime. Conversely, the density of energy sources is only expected to slightly increase. In front of this scenario, there exists a demand in improved power management integrated circuits to avoid a powering crisis in future systems-on-chip. The ultimate step consequently consists in the fully monolithic integration of the power converter together with the circuits that constitute its load within either the same substrate or chip package, yielding a complete Powered System on a Chip (PSOC). This lecture will cover efficient energy processing circuits within an integrated circuit environment, which requires a multidisciplinary approach through concurrence of analog and mixed-signal IC design, power electronics and control theory disciplines. Topics covered will encompass on-chip power supply design and implementation, efficiency optimization, IC-compatible power inductors and capacitors, power MOSFET switches and efficient switch drivers, analog current-mode controller IC design, digital controllers, system and circuit-level design of on-chip adaptive power management techniques, adaptive wideband envelope-tracking power supplies for RF power amplifiers, and adaptive voltage scaling for low-power microprocessor and DSP supply.

Biography

Eduard Alarcón (S'96, M'01) received the M. Sc. (national award) and Ph.D. degrees in electrical engineering from the Technical University of Catalunya (UPC), Barcelona, Spain, in 1995 and 2000, respectively. Since 1995 he has been with the Department of Electronic Engineering at the Technical University of Catalunya, where he became Associate Professor in 2000. During the period 2006-2009 he has been Associate Dean of International Affairs at the School of Electrical Engineering, UPC. From August 2003 to January 2004, he was a Visiting Professor at the CoPEC center, University of Colorado at Boulder, USA. He has co-authored more than 130 international scientific publications, 3 book chapters and 2 patents, and has been involved in different national and US R&D projects. His current research interests include the areas of analog and mixed-signal integrated circuits, on-chip power management circuits, wireless energy transfer and nanonetworks. He has given 12 invited or plenary lectures and tutorials in Europe, America and Asia, and has been elected by the IEEE CAS society as distinguished lecturer for 2009-2010. He was recipient of the Myril B. Reed Best Paper Award at the 1998 IEEE Midwest Symposium on Circuits and Systems. He was the invited co-editor of a special issue of the Analog Integrated Circuits and Signal Processing journal devoted to current-mode circuit techniques, and a special issue of the International Journal on Circuit Theory and Applications. He co-organized two special sessions related to on-chip power management at IEEE ISCAS03 (Bangkok, Thailand) and IEEE ISCAS06 (Kobe, Japan) and a tutorial at IEEE ISCAS09 (Taipei, Taiwan). He was the 2007 Chair of the IEEE Circuits and Systems Society Technical Committee of Power Systems and Power Electronics Circuits. He was the technical program co-chair of the 2007 European Conference on Circuit Theory and Design - ECCTD07 (Seville, Spain), track chair of the IEEE ISCAS 2007 (New Orleans, US), IEEE MWSCAS07 (Montreal, Canada), IEEE ISCAS 2008 (Seattle, US), ECCTD’09 (Antalya, Turkey) and IEEE MWSCAS09 (Cancun, Mexico). He served as an Associate Editor of the IEEE Transactions on Circuits and Systems - II: Express briefs (2006-2007) and currently serves as Associate Editor of the Transactions on Circuits and Systems – I: Regular papers (2006-2009).