Tuesday, February 13th, 2007 IEEE SCV EDS Meeting:

"Recent Progress in Photovoltaics - An IMEC view"

Speaker: Dr. Robert Mertens - IMEC, Belgium
Subject: "Recent Progress in Photovoltaics - An IMEC view"
Location: National Semiconductor Building E Auditorium,
      2900 Semiconductor Drive, Santa Clara, CA 95051.  
      See the NSC Campus driving directions
      and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: Philippe Jansen - IMEC

Abstract:

The European vision on the cost and market evolution of photovoltaics will be explained. The solar cell roadmap of IMEC will be presented. The IMEC work on crystalline silicon and organic cells will be covered.

In the field of wafer-based industrial crystalline silicon cells, an evolutionary path towards thinner and therefore cheaper cells will be highlighted. Efficient epitaxially grown silicon solar cells and very thin (5 mm thick) crystalline silicon cells on glass or ceramic substrates will be discussed. These very thin cells are based on a lift-off approach or an aluminum-induced crystallization.

In organic solar cells, IMEC is concentrating on bulk donor-acceptor heterojunctions based on P3HT: PCBM for which state-of-the-art results, ie. an efficiency of 4.3 percent, will be reported. The importance of the blend ratio and the kind of solvent used will be illustrated in the talk.

Biography:

Robert P. Mertens received the Electrical Engineering (MSEE) and Ph.D. degrees from the Catholic University of Leuven, Belgium, in 1969 and 1972 respectively. He was a visiting scientist at the University of Florida in 1973.

After his return to Belgium in 1974, he became a senior research associate of the National Foundation for Scientific Research of Belgium.

In 1984 he joined the Interuniversity Microelectronics Center (IMEC) as research manager for materials research and packaging. Until December 2006, he was the Senior Vice President of IMEC for Micro-Systems, Components, and Packaging.

Today he is a IMEC Senior Fellow and Senior Vice President for IMEC's Scientific Leadership team. Since 1984 he has been a professor at the University of Leuven, where he is teaching courses on semiconductor devices and on the technology of electronic and optoelectronic systems.

He was elected Fellow of the IEEE for contributions to heavily-doped semiconductors, bipolar transistors, and silicon solar cells. He has authored or co-authored more than 300 publications, has received several best paper awards, and has been program chair of several technical conferences.

For more information on   IMEC - Belgium

For more information on the   IMEC Research Activities

Thursday, February 15th, 2007 IEEE SCV SSC Meeting:

"RF ESD Protection Strategies: The Design and Performance Trade-off Challenges"

Speaker: Dr. Philippe Jansen - IMEC
Subject: "RF ESD Protection Strategies: The Design and Performance Trade-off Challenges"
Location: National Semiconductor Building E Auditorium,
      2900 Semiconductor Drive, Santa Clara, CA 95051.  
      See the NSC Campus driving directions
      and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: Philippe Jansen - IMEC

Abstract:

Emergence of extensive applications for portable electronics has fueled the rapid deployment of CMOS and BiCMOS based integrated RF front-ends.

These technologies demonstrate device carrier transit frequencies well above 150 GHz, e.g. with transistors in a typical 90nm CMOS technology, and are commercially available for manufacturing.

On the other hand, implementing Electrostatic Discharge (ESD) protection on these RF front-end designs, such as Low Noise Amplifiers (LNA), is essential to ensure reliable operation.

The ESD protection strategies for RF circuits reported in the literature include, but are not limited to classical diodes with power clamps, inductors with power clamp, distributed ESD protection using transmission lines or coplanar wave guides, resonant and cancellation methods, and ESD-RF co-design techniques.

All these techniques, except the first one, mark a paradigm shift in the ESD protection strategies specifically for high frequency circuit applications. It is also important to note that the protection strategies described above may not be useable in all cases and only a few reports show silicon validation data, especially for sub-130nm technologies.

Abstract (Continued):

This presentation presents the results of a thorough investigation carried out on four ESD protection strategies in CMOS and BiCMOS technologies to obtain a clear understanding of the possible trade-offs in both RF and ESD design.

This is achieved through design and evaluation of RF and ESD performances for a generic LNA, in which the RF pin is protected using different ESD protection approaches.

Biography:

Philippe Jansen received his M.Sc. and PhD in electrical engineering from K.U. Leuven, Belgium in collaboration with IMEC in 1988 and 1993 respectively.

He has performed post-doctoral research at the Hitachi Central Research Laboratory in Tokyo, Japan. Since 1994, he has worked for IMEC on various topics: advanced CMOS and BiCMOS integration, electrostatic discharge (ESD) protection, and advanced packaging.

Currently, his interests are in advanced BiCMOS process integration, ESD protection for RF circuits, and integrated package research and development.

Moreover, he is also in charge of the IMEC business development office in the USA. The IMEC USA office is located in San Jose, CA.

For more information on   IMEC - Belgium

For more information on the   IMEC Research Activities

Details:

A No Cost IEEE SCV EDS Mini-Colloquium will be held on the Santa Clara University campus, Santa Clara, CA on Friday, February 23, 2007. This colloquium will be sponsored by the IEEE Electron Devices Society and hosted by the local IEEE SCV Electron Devices Society Chapter and the staff and students of the Santa Clara University Electrical Engineering Department.

This symposium will feature an invited list of distinguished Electron Devices Society lecturers. The main focus of the colloquium is to learn about recent advances in the field of nanoscale semiconductor devices and their related process technologies.

A light lunch will be served during the mid-day break.

Light refreshments will be served at the mid-afternoon break.

Please RSVP to the email address shown above if you wish to attend this event.

9:30 AM   Registration
9:45 AM   Welcome and Introduction
          ·   Professor Cary Yang, Santa Clara University
          ·   Dr. Philippe Jansen, IEEE SCV EDS Chapter Chair

The currently scheduled Mini-Colloquium speakers and speaker topics are as follows:

Morning Session Chairs: Professor Shoba Krishnan and Dr. Jayasimha Prasad

10:00 AM   Strain Engineering and Device Performance: Benefit or Compromise?
          ·   Professor Cor Claeys, IMEC, Belgium
10:50 AM   Robust Electrostatic Discharge (ESD) Protection in CMOS Technology
          ·   Professor Juin J. Liou, University of Central Florida, Orlando, Florida
11:40 AM   High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs
          ·   Dr. Tejas Krishnamohan, Intel

12:30 PM - Lunch Break and Student Poster Presentations

Afternoon Session Chairs: Dr. Samar Saha and Dr. Philippe Jansen

1:50 PM   RCL Characterization and Modeling of X Architecture Diagonal Wires for VLSI Design
          ·   Dr. Narain Arora, Cadence Design Systems
2:40 PM   Recent Advances in Photonic Devices for RF/Wireless Communication Applications
          ·   Professor Paul K. L. Yu, UC San Diego

3:30 PM - Afternoon Coffee Break

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