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Santa Clara Valley Chapter
http://www.ewh.ieee.org/r6/scv/eds/
The field of interest of the IEEE EDS is all aspects of the physics, theory, and phenomena of electron and ion devices, such as elemental and compound semiconductor devices, quantum effect devices, optical devices, tubes and other vacuum devices.

Please Post and Circulate within your Company. 		April 1, 2007
For an online version of this announcement with active links, please visit
http://www.ewh.ieee.org/r6/scv/eds/announcements/ieee-scv-eds-20070401.html
April 10th Meeting
Dr. Albert Bergemont - Maxim
"Current Limitations of Floating Gate NVM and New Alternatives"

 

 

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Albert-Bergemont-Maxim.jpg Upcoming IEEE SCV EDS Evening Meeting:

Tuesday, April 10, 2007 IEEE SCV EDS Meeting:

"Current Limitations of Floating Gate NVM and New Alternatives"

Speaker: Albert Bergemont - Maxim Integrated Products
Subject: "Current Limitations of Floating Gate NVM and New Alternatives"
Location: National Semiconductor Building E Auditorium,
      2900 Semiconductor Drive, Santa Clara, CA 95051.  
      See the NSC Campus driving directions
      and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: Jayasimha Prasad

Abstract:

This talk will review the expected flash memory scaling limits below 45 nanometers and present the most promising emerging flash memory technologies for mass storage applications.

Floating gate flash memory scaling has been phenomenal in the last 15 years. As a result, the overall flash memory market has grown at an unprecedented pace, mainly driven by exploding customer demand for mobile mass storage applications such as digital cameras, MP3 players, and cell phones.

In such a large commodity market, the course for further flash memory cell scaling has led to tremendous R&D activity in the last few years with NAND density doubling almost every year.

Although it is expected that flash memory cells will continue to scale, there are several physical limitations to confront, and scaling down beyond 45nm is a concern, especially for the floating gate memory architectures.



Upcoming IEEE SCV EDS Evening Meeting:

Biography:

Albert Bergemont was born in Toulouse, France, in 1953. He graduated from the French National Institute of Applied Sciences, where he received the B.S degree in Physics and Solid State Physics in 1975.

Up to 1995, he was mainly involved with technology development of non-volatile technologies (stand-alone EEPROM, EPROM, FLASH) successively at Harris Semiconductor (first CMOS EEPROM, ahead of Intel), SGS-THOMSON Micro (several NVM platforms from 0.8µm down to 0.35µm) and National Semiconductor (first AMG EPROM with Boaz Eitan, and first contact-less NOR Virtual Ground Flash, using channel erase, ahead of all the other semiconductor industry players.

From 1995 to 2000 at National Semiconductor, he also developed and transferred successfully to production three generations of core CMOS and mixed-mode modules down to 0.18µm.

He invented and demonstrated ahead of all the industry the free P-channel OTP and MTP concepts, now widely used worldwide. He also developed with Carver Mead the first Active Pixel Sensor CMOS imager (0.18µm), while the rest of the world was still using CCDs.

He joined Maxim Integrated Products in 2000, where he is currently the TR&D Executive Director. He is in charge of core analog CMOS/Bipolar/HV technology platforms which also feature embedded NVM (EEPROM and Flash).

He has authored and co-authored around 50 technical papers.

He currently holds 181 patents with a few more pending at Maxim.



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