
	Electron Devices Society Santa Clara Valley Chapter http://www.ewh.ieee.org/r6/scv/eds/


The field of interest of the IEEE EDS is all aspects of the physics, theory, and phenomena of electron and ion devices, such as elemental and compound semiconductor devices, quantum effect devices, optical devices, tubes and other vacuum devices. Please Post and Circulate within your Company.	January 8, 2008
For an online version of this announcement with active links, please visit http://www.ewh.ieee.org/r6/scv/eds/announcements/ieee-scv-eds-20080114.html

January 14th Meeting
Charvaka Duvvury, Texas Instruments
"Silicon Technology Scaling and ESD Challenges"

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Upcoming IEEE SCV EDS Evening Meeting:

Monday, January 14, 2008 IEEE SCV EDS Meeting:

"Silicon Technology Scaling and ESD Challenges"

Speaker: Charvaka Duvvury, Texas Instruments
Subject: "Silicon Technology Scaling and ESD Challenges"
Location: National Semiconductor, Building E1, Conference Center,
2900 Semiconductor Drive, Santa Clara, CA 95051.
See the NSC Campus driving directions
and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: Ranjeet.K.Pancholy

Abstract:

The trends in the silicon technology scaling towards the sub-100 nm range, along with the introduction of newer transistor structures such as the multi-gate and Fin FET devices, are driving sensitive issues for ESD development and IC protection design. This is compounded by the complex interactions from aggressive circuit design improvements that include high speed applications, 3.3V and 5V analog functions in 90nm and 65nm technologies, and other mixed voltage applications. Even more complex is the System-on-Chip (SoC) that integrates RF, Analog and Digital functions on the same chip, and more recently the stacked die and stacked package approaches.This presentation will first examine the advances in transistor structures and their impact on intrinsic ESD robustness. This will be followed by a summary of the issues related to the new effects of IC packages. Finally, the ESD technology road map and the practical methods that should be followed to maintain ESD reliability into the next decade will be offered.

Upcoming IEEE SCV EDS Evening Meeting:

Biography:

Charvaka Duvvury is a Texas Instruments Fellow working in the Silicon Technology Development group at Dallas. He has more than 25 years of experience in the semiconductor industry with specific work on advanced silicon technology research and development. His current work is on development and companywide support on Electrostatic Discharge (ESD) for the nanometer submicron CMOS technologies.

Charvaka received his Ph.D. in Engineering Science from the University of Toledo. He has published over 120 papers in technical journals and conferences and holds 60 patents with several pending. He has co-authored three books on transistor reliability, modeling for electrical overstress, and ESD design.

He has been very active in the ESD Symposium where he was the General Chairman both in 1994 and in 2005. He is a Director on the ESD Association Board since 1997 promoting university advanced research in ESD. He is a recipient of the Outstanding Contributions Award from the ESD Association. Charvaka is a member of the Electron Devices Society and is a Fellow of the IEEE.

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