
	Electron Devices Society Santa Clara Valley Chapter http://www.ewh.ieee.org/r6/scv/eds/


The field of interest of the IEEE EDS is all aspects of the physics, theory, and phenomena of electron and ion devices, such as elemental and compound semiconductor devices, quantum effect devices, optical devices, tubes and other vacuum devices. Please Post and Circulate within your Company.	January 8, 2008
For an online version of this announcement with active links, please visit http://www.ewh.ieee.org/r6/scv/eds/announcements/ieee-scv-eds-20080122.html

January 22nd Meeting
Dr. Bin Yu, NASA Ames Research Center
"IC Chips - from Scaling to Emerging Nanotechnology"

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Upcoming IEEE SCV EDS Evening Meeting:

Tuesday, January 22, 2008 IEEE SCV EDS Meeting:

"IC Chips - from Scaling to Emerging Nanotechnology"

Speaker: Dr. Bin Yu, NASA Ames Research Center
Subject: "IC Chips - from Scaling to Emerging Nanotechnology"
Location: National Semiconductor, Building E1, Conference Center,
2900 Semiconductor Drive, Santa Clara, CA 95051.
See the NSC Campus driving directions
and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: J. Prasad

Abstract:

It is predicted that silicon CMOS FET could be ultimately scaled down to 1.5 nm gate length based on the least energy model for computing. However, it is anticipated that a gate length of 4~5 nm would be the practical limit (in mass production around year-2020). In this seminar, some major trends will be discussed of the mainstream IC chip technology in the next 1½-decade towards the “scaling-end” of ITRS Roadmap. There are technology candidates that are of strategic importance beyond the Roadmap. Some were actively explored in research community for long, while a few others were catching up rapidly.

“Bottom-up” approach, the core concept of nanotechnology, is to employ inexpensive chemistry to promote self-assembly of mesoscopic architectures. Nanostructures offer unique properties such as energy efficiency, surface sensitivity, self-assembly, low material/processing cost, etc., that could be the valuable building blocks for the next-generation electronic chips. In this seminar, we discuss some potential “successors” of the concurrent silicon chip technology at the end of Semiconductor Roadmap. These disruptive technologies are rooted in nanoscale materials or structures -synthesized by inexpensive chemistry - which exhibit exceptional materials and electrical properties. The new technologies would help continued advancement, not necessary through straightforward geometry scaling, of solid-state chip technology in applications such as information processing and nonvolatile data storage. The state-of-the-art research in the front will be introduced. Major challenges and future directions will be also discussed.

Upcoming IEEE SCV EDS Evening Meeting:

Biography:

Dr. Bin Yu received Ph.D. degree in Electrical Engineering from University of California at Berkeley. At Berkeley, he conducted research on semiconductor device physics, scaling, and ultra-thin-body SOI technology. His research interest spans from self-assembly of functional nanostructures to emerging applications in information processing, storage, and transmission.

He is presently Senior Scientist at UARC, NASA Ames Research Center. Before that, he led exploratory device research at Advanced Micro Devices Inc., Sunnyvale, CA, with focus on novel device architectures and advanced technologies for high-performance microprocessors.

His technical accomplishments include industry’s first 10-nm silicon double-gate transistor (IEDM'2002), the industry's first Tera-Hz 15-nm planar silicon logic transistor (IEDM'2001), the record-thin gate dielectric for CMOS (VLSI'2001), the first demonstration of laser thermal process in nanoscale CMOS (IEDM'1999), among others. Some of these breakthroughs were widely reported by public media around the world. He has published over 80 research papers, delivered about 40 invited talks to conferences, industry, and universities, and holds more than 100 awarded U.S. patents.

He is AdCom Member of IEEE Nanotechnology Council and Ex-Officio AdCom Member of IEEE Electron Device Society, and served on technical committees, advisory committees, and invited rump-session panels of numerous conferences and organizations, including National Nanotechnology Initiative/SRC Consultative Group and International Roadmaps for Semiconductors. He served also as consultant to semiconductor companies and venture capital firm in Silicon Valley. He is IEEE-EDS Distinguished Lecturer, Editor of IEEE Electron Device Letters, Associated Editor of IEEE Transactions on Nanotechnology, and Consulting Professor of Electrical Engineering at Stanford University. He was elected IEEE Fellow for recognized accomplishments in semiconductor nanoelectronics.

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