Upcoming IEEE SCV EDS Evening Meeting:
Tuesday, March 18, 2008 IEEE SCV EDS Meeting:
"The promise of high-K/metal gates – From electronic transport phenomena to emerging device/circuit applications"
Speaker: Dr. Kingsuk Maitra, AMD
Subject: "The promise of high-K/metal gates – From electronic transport phenomena to emerging device/circuit applications"
Location: National Semiconductor, Building E1, Conference Center,
2900 Semiconductor Drive, Santa Clara, CA 95051.
See the NSC Campus driving directions
and the NSC Building E location map
Time: 6:30 PM - Pizza , 7:00 PM - Lecture
Speaker Contact:
Manuj Rathor
Abstract:
Recent advancements of gate stack engineering have enabled the introduction of
high-K/metal gates into mainstream CMOS device applications for 45 nm and beyond
technology space.
In this talk, we take a critical look back into the key steps
which made this possible with primary focus on transport phenomena in transistors
in presence of high-K/metal gates. Against this backdrop, the interaction of
high-K/metal gates with end of roadmap devices would be thoroughly explored.
High-K/metal gates have interesting ramifications in the circuit space-from NBTI
(negative bias temperature instability) to high-field mobility,
|
|
Upcoming IEEE SCV EDS Evening Meeting:
the high-K gate induced physical phenomena and their impact on device and circuit
performance and reliability would be discussed.
To conclude, this talk would also conjecture on
the continued scalability of high-K gate stacks for futuristic CMOS device
architectures.
Biography:
Kingsuk Maitra graduated with a PhD in Electrical Engineering from the Department of
Electrical and Computer Engineering, NC-State University, Raleigh in
December 2005 where he worked on electronic transport in bulk-Si nMOSFET’s in presence
of high-K gate insulator. He also holds a Masters degree in Microelectronics from the
Indian Institute of Science, Bangalore, India and a Masters degree in Physics from
the University of Kalyani, India.
He is currently working as a Senior Technology and Integration Engineer with AMD for
the IBM/AMD pre-T0 Research alliance at Albany Nanotech, NY. His current work focuses
on finding device solutions for 22 nm Technology node. As a PhD student, he worked as
a summer intern for three summers (2003, 2004, and 2005) with the Advanced Gate stack
team at IBM Research, IBM TJ Watson Research Center at Yorktown Heights on high-K gate
dielectric based devices.
His research interests also include transport phenomena in end of roadmap CMOS
devices, gate stack engineering in nanometer scale devices for future electronic
applications.
|