Wednesday, June 4, 2008 IEEE SCV EDS Meeting:

"Development of a Technology Platform for Nano-scale RF SoC Design"

Speaker: Dr. Yuhua Cheng, ShangHai Research Institute of MicroElectronics (SHRIME), Peking University
Subject: "Development of a Technology Platform for Nano-scale RF SoC Design"
Location: National Semiconductor, Building E1, Conference Center,
      2900 Semiconductor Drive, Santa Clara, CA 95051.  
      See the NSC Campus driving directions
      and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: Philippe Jansen

Abstract:

This talk discusses the technology platform development for IC design in nano-CMOS technologies. New effects and issues in nano-CMOS are reviewed before the discussion on the contents of the technology platform. Some key components are briefly discussed with the exploration of some further challenges to develop a RF SoC design technology platform. An advanced technology platform with strong links to process and device behavior and efficient simulation approaches is critical to a successful advanced IC design in nano-scale CMOS technologies.

Biography:

Yuhua Cheng received the B.S. degree (Honored) in Electrical Engineering, Shandong Polytechnic University (now Shandong University), Jinan, China in 1982, the M. S. degree in Electrical Engineering, Tianjin University, Tianjin, China in 1985, and the Ph.D. degree in Electrical Engineering, Tsinghua University, Beijing, China in 1989.

In 1990, he joined in the Institute of Microelectronics (IME), Peking University, China. From 1992 to 1996, he was an associate professor in IME. From 1994 to 1995, he worked at the Norwegian University of Science and Technology, Trondheim, Norway, as a Visiting Professor and a Research Fellow of the Norwegian National Research Council. From 1995 to 1997, he was a Senior Research Scientist at the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, where he was working on the development of BSIM3v3 (Berkeley Short-channel IGFET Model 3 version 3). He was the project coordinator and one of the principal contributors of the BSIM3v3, which was chosen as the first industry standard compact model for IC simulation by Electronics Industry Association/Compact Model Council and given an R&D 100 Award in 1996.

In 1997, he worked at Cadence Design Systems and then joined Rockwell International. From 1997-2004, he worked at Rockwell Semiconductor Systems, Conexant Systems (a spin-off from Rockwell), and Skyworks Solutions (a spin-off from Conexant), where he was a Principal Engineer, a Manager, and a Senior Manager. Under his leadership the Skyworks technology group was expanded into a strong engineering team that plays a key role in developing Mixed-signal/RF technology for various (ASIC, analog, Mixed-signal, RF) circuit designs. From 2004-2006, he worked in Siliconlinx, Inc., which offers products and services to bridge the gap between IC designers and manufacturing foundries. He is now a full professor in Peking University and the Dean of a newly established research institute of microelectronics in Shanghai.

He has served on many Technical Program Committees and chaired numerous Sub-committees at international conferences, including the IEEE Custom Integrated Circuits Conference (CICC) since 2001 and Radio Frequency Integrated Circuits Symposium since 2002.  He organized and participated in numerous workshops and panels related to RFCMOS technology and SoC design. He has authored and co-authored over 90 research papers, two book chapters, two books “MOSFET Modeling & BSIM3 User’s Guide” by Kluwer Academic Publishers (1999), and   “Device modeling for analog/RF circuit design” by John Wiley and Sons (2002).

He is an IEEE fellow and an IEEE Distinguished Lecturer of EDS. His research interests include advanced RFCMOS technology, analog/mixed-signal/RF circuit designs for system integration applications.

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