Thursday, August 28, 2008 IEEE SCV EDS Meeting:

"Development and Challenges on Reliability Characterization of CMOS Devices with Gate Oxide in the Tunneling Regime"

Speaker: Dr. Steve S. Chung, National Chiao Tung University, Taiwan
Subject: "Development and Challenges on Reliability Characterization of CMOS Devices with Gate Oxide in the Tunneling Regime"
Location: National Semiconductor, Building E1, Conference Center,
      2900 Semiconductor Drive, Santa Clara, CA 95051.  
      See the NSC Campus driving directions
      and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: Samar Saha

Abstract:

Conventional CV method has been used for almost over 4 decades, in which it needs a large area capacitor for the measurement and has faced difficulties when gate leakage current exists. Several other gate oxide reliability analysis techniques, such as CP (Charge-Pumping), GD (Gated-Diode), DCIV etc. have been elaborated for similar purpose. However, as device gate oxide thickness keeps shrinking to the direct-tunneling regime (e.g., <20A), it reaches a limit for the measurement as a result of direct tunneling gate leakage and the quantum mechanical effect. This talk will give an overview of previous and the current measuring techniques for the process and reliability characterization to state-of-the-art CMOS devices. Its potential use for the device hot carrier reliability study, NBTI, and process characterization, e.g., oxide quality monitor, interface profiling, HC stress effect etc., will be presented. More recent developments for 1nm range ultra-thin gate oxide CMOS device applications will also be demonstrated. In particular, more recent applications to the reliability study of strained-silicon CMOS devices will be described. Further development and the road blocks of these techniques will be addressed.

Biography:

STEVE S. CHUNG received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering in 1985. His Ph.D. thesis advisor is the world-famous scholar and CMOS Co-Inventor, Prof. C. T. Sah. He joined National Chiao Tung University (NCTU) in 1987 and currently, a Chair Professor and UMC Research Chair Professor at NCTU. In 2007-2008, he has been the Dean of International Affairs at NCTU. Between 2004-2005, he was the first Department Head of EECS Honors Program, to promote an undergraduate program for academic excellence. He has been a Research Visiting Scholar with Stanford University in 2001. He was also the consultant to the two world largest IC foundries, TSMC and UMC, on developing CMOS and flash memory technologies. His current research areas include CMOS devices; flash memory, and reliability characterization; and nano-science in bio applications. He has published more than 160 journal and conference papers, one textbook, and holds 20 patents. From 1995-2008, he presented more than 15 times in the prestigious IEEE conferences, IEDM and VLSI.

He is an IEEE Fellow, AdCom member, Distinguished Lecturer, Regions/Chapters Vice-Chair of EDS, and Editor of EDL. He has served on the committees of premiere conferences, e.g., VLSI Technology, IEDM, IRPS, etc. ED Taipei chapter was awarded the 2002 EDS Chapter of the Year Award under his leadership as the chapter chair. He was awarded 3 times outstanding Research Award for excellence in research, as well as the top-PI in 2003, from the National Science Council. He was also granted Distinguished EE Professor and Engineering Professor by the Engineering Societies of Taiwan.

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