
	Electron Devices Society Santa Clara Valley Chapter http://www.ewh.ieee.org/r6/scv/eds/


The field of interest of the IEEE EDS is all aspects of the physics, theory, and phenomena of electron and ion devices, such as elemental and compound semiconductor devices, quantum effect devices, optical devices, tubes and other vacuum devices. Please Post and Circulate within your Company.	November 1, 2008
For an online version of this announcement with active links, please visit http://www.ewh.ieee.org/r6/scv/eds/announcements/ieee-scv-eds-20081101.html

November 11th Meeting
Dr. Brian Chen, Synopsis
"Spice Model Extraction for Partially-Depleted SOI Technologies in Concurrent Designs"

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Upcoming IEEE SCV EDS Evening Meeting:

Tuesday, November 11, 2008 IEEE SCV EDS Meeting:

"Spice Model Extraction for Partially-Depleted SOI Technologies in Concurrent Designs"

Speaker: Dr. Brian Chen, Synopsis
Subject: "Spice Model Extraction for Partially-Depleted SOI Technologies in Concurrent Designs"
Location: National Semiconductor, Building E1, Conference Center,
2900 Semiconductor Drive, Santa Clara, CA 95051.
See the NSC Campus driving directions
and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: Manuj Rathor

Abstract:

Spice model extraction for partially-depleted (PD) silicon-on-insulator (SOI) technologies needs to address a number of technical challenges on top of those encountered in conventional bulk CMOS. They include the self-heating effect, characterization and modeling of the floating-body voltage, and its related circuit-level model validation. Model extraction is further complicated by the necessity to support concurrent designs when little or very limited silicon (hardware) data is available. This talk will provide a brief overview of PD SOI Spice model extraction with examples of several 90nm and 65nm case studies from various stages of model extraction, including data analysis, device-level model validation, and circuit-level model validation.

Upcoming IEEE SCV EDS Evening Meeting:

Biography:

Brian (Qiang) Chen received his B.S and M.S. in Engineering from Saint-Petersburg Electrotechnical University (‘LETI’), Saint-Petersburg, Russia, and M.S. and Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology, Atlanta, Georgia. He held positions in RIE process development and lithography section management at Korona Semiconductor, a foundry in Zelenograd, Russia. At Advanced Micro Devices, Brian contributed to Spice model extraction methodology and infrastructure development as well as model production from 90nm through 32nm nodes. Currently, he is working on Design for Manufacturing (DFM) flow optimization at Synopsys.

Brian has served on the Technical Program Committee of IEEE Custom Integrated Circuit Conference since 2007.

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