Tuesday, January 20, 2009 IEEE SCV EDS Meeting:

"Ramping 32 nm High-Volume Manufacturing of Performance Logic in Record Time"

Speaker: Dr. Hans Stork, Applied Materials
Subject: "Ramping 32 nm High-Volume Manufacturing of Performance Logic in Record Time"
Location: National Semiconductor, Building E1, Conference Center,
      2900 Semiconductor Drive, Santa Clara, CA 95051.  
      See the NSC Campus driving directions
      and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: Reza Arghavani

Abstract:

The transition to 32nm is happening as scheduled with 1.2 numerical aperture (NA) immersion lithography ready. There will not be disruptive technologies such as new substrates, biaxial stress and double gates—rather, 32nm will continue to use bulk silicon, uniaxial stress, high-k/metal gates and planar transistors. In this landscape, Applied Materials is focusing on materials innovation, cost of ownership and ease of transition to high volume manufacturing.

Continuous device scaling requires an increase in gate dielectric capacitance in order to control short channel effects. The 90nm logic node thus reached the final scaled gate with oxynitride dielectric at 1.2nm. The 65nm logic node continued with this gate dielectric and minor gate CD scaling but integrated more strain inducing layers into the process flow. The 45nm node introduced the first high-k and metal gates in high volume manufacturing. The implementation of high-k and metal gate adds new metrology, chemical mechanical polish (CMP) and etch challenges due to introduction of new materials and integration approaches. The industry has adopted uniaxial stress using two types of techniques: (i) stress inducing films such as the dual stress liner approach (DSL), which integrates compressive and tensile nitride films and (ii) embedded epitaxial films in the source/drain. The various strain engineering options can be combined and have proven to be additive. For the 32 nm node, the poly CD will be ~30 nm with a contacted-gate-pitch of ~120 nm. Pitch scaling, which is required for cost reductions, leads to increased external resistance which is opposite to the decreasing trend of the strain engineered channel resistance.

Significant breakthroughs emerged in logic transistor technology in the past decade. Introduction of uniaxial strain at 90nm logic node and combination of mobility enhancing stressors boosted logic cell performance to meet 32nm node requirements. Reliable gate oxynitride of only a few atomic monolayers are routinely introduced in high volume manufacturing. Introduction of high-k/metal gates was debuted as the biggest change in the past four decades. This talk reviews the material, integration method and tool sets best suited for integration of the 32nm high performance logic technology node in high volume manufacturing.

Biography:

Dr. Hans Stork was named chief technology officer and group vice president for the Silicon Systems Group at Applied Materials in October 2007, where he is responsible for leading the company’s roadmap for silicon technology equipment. In this role, Dr. Stork oversees integrated technology development across the silicon products, coordinates the organization’s industry and university engagements and ensures value to customers by leveraging understanding of technology interactions to optimize differentiated product solutions.

Prior to joining Applied Materials, Dr. Stork served as CTO and senior vice president of Silicon Technology Development for Texas Instruments from 2001 to 2007. He served as lab director for ULSI and Storage & Systems Labs for Hewlett Packard from 1994 to 2001, and was senior manager for Exploratory Si Technology at IBM from 1982 to 1994, where he received two outstanding achievement awards.

Dr. Stork is an IEEE Fellow and member of the board of directors for Semiconductor Research Corporation and the Semiconductor Industry Association technology strategy committee. He previously served as a member of the advisory committee for the Texas State Emerging Technology Fund from 2005 to 2006 and was a member of the board of directors for Sematech from 2002 to 2007.

Dr. Stork earned both a bachelor of science and Diplom-Ingenieur degree in electrical engineering from Delft University of Technology, The Netherlands. He earned his doctorate in electrical engineering from Stanford University.

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