
	Electron Devices Society Santa Clara Valley Chapter http://www.ewh.ieee.org/r6/scv/eds/


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Upcoming IEEE SCV EDS Evening Meeting:

Tuesday, May 12, 2009
"Power and variability: challenges and solutions"
Dr. Subramanian "Shiva" Ramesh, CTO GreenSys Technologies

Location: National Semiconductor, Building E1, Conference Center,
2900 Semiconductor Drive, Santa Clara, CA 95051.
See the NSC Campus driving directions
and the NSC Building E location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact: Ranjeet Pancholy

Abstract:

The many-dimensional challenge of power/energy efficiency has become urgent and critical not just for the electronics and semiconductor industries but also for society as a whole. At the macroscopic level, in terms of impacting the environment, one example of the magnitude of the problem is that a typical large data-center today consumes 5MW - and the number, size and power-consumption of data-centers is growing rapidly around the world. In order to achieve substantial energy-efficiency at the data-center level, clear technical analyses and solutions are needed at all levels and especially the connectivity between the levels (data-center to system to chip to IP). GreenSys Technologies intends to contribute by providing technical solutions to some of these key problems.

Per request of the organizers, for this IEEE lecture I will go deeper into the major power-related challenges at the System-on-Chip (SOC) level and below. Over the last few years, various solutions for power-reduction at IP-level and chip-level have been proposed or implemented by a number of chip companies. Analysis of which techniques work and how well is complex and involves a number of competing factors including understanding the intended application(s); one aspect that has often been ignored is the connection between power challenges/solutions and process variability. Ever-increasing variability in sub-65nm technology nodes leads to a longer "tail" of power-dissipation that must be accounted for to satisfy the intended product specifications. Process-induced variability is commonly mitigated through careful layout practices (e.g. channel length, orientation, layout pitch restrictions), but it has also required innovative design techniques. Variability and power dissipation are interdependent in another sense: techniques intended to reduce power such as Dynamic Voltage Scaling (DVS) and Adaptive Body Biasing (ABB) need to account for increased on-chip variability. Especially in 45nm node and below, aggressive use of some techniques can cause functionality issues in silicon. I will discuss a special chip that I led the architecture/design of (in my recent position) that was specifically meant to deconvolute the effects of power and variability and will discuss the 45nm-node silicon data/analysis. His paper received Best Paper Award at ISQED, March 2009.

Upcoming IEEE SCV EDS Evening Meeting:

Biography:

Subramanian "Shiva" Ramesh, Ph.D. is currently founder and CTO of GreenSys Technologies focusing on power/energy efficiency solutions. Until recently he was Senior Engineering Director at LSI Corporation where he led the Advanced Technology & Architecture team and other technical management roles. While his recent work at LSI focused on the critically important areas of power and variability, Dr. Ramesh has previously made many innovative contributions to embedded memory IP development, leading the industry in robust, high-density, low-power memories and bitcells. Prior to LSI, Dr. Ramesh worked at NEC and NTT in Japan (doing R&D in the Japanese language!), was visiting research faculty at North Carolina State University, and worked at Philips Research.

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