SCV EDS Meeting “NBTI”- June 9th (Tuesday), 2009

Tuesday, June. 9, 2009 IEEE SCV EDS Meeting

" Negative Bias Temperature Instability in p-MOSFETs: Fundamentals, Characterization, Materials Dependence and Modeling”

Location: National Semiconductor, Building E1, Conference Center ,
2900 Semiconductor Drive , Santa Clara , CA 95051 .  
See the NSC Campus driving directions
See the NSC Building location map

Time: 6:00 PM - Pizza , 6:15 PM - Lecture

Speaker: Dr. Souvik Mahapatra, Dept. of Electrical Engineering, IIT Bombay

Speaker Contact: Prasad Chaparala

 

Abstract:
Negative Bias Temperature Instability (NBTI), causing shifts in device parameters such as drain current and threshold voltage, is a serious reliability concern for p-MOSFETs. Though identified more than 40 years ago, NBTI has become the most severe front end reliability issue only recently, as gate oxide thickness is scaled below 2nm, and Nitrogen is incorporated into the gate oxide to prevent Boron penetration and leakage. Besides Si oxynitride/poly-Si devices, NBTI is also a serious concern for high-k/metal gate devices as well.

Like other reliability issues (like HCI), device lifetime under NBTI is determined by accelerated stress tests done at short time, and extrapolating the degradation under operating condition to end of life. It is very important to choose proper stress condition such that defects responsible for NBTI are only accelerated and no new defects are formed. As NBTI degradation recovers (unlike HCI) after stress is turned off for measurement, conventional stress-measure-stress methods give erroneous results, and fast methods must be implemented. It is important to understand and model NBTI physical mechanism, so that proper physics-based models can be developed for reliable determination of device lifetime. It is also important to understand the process / material dependence of NBTI to develop robust, NBTI safe gate insulators that meet other (leakage, mobility) requirements. The talk will address some of these issues.

Biography:
Souvik Mahapatra received his Ph.D. in Electrical Engineering from Indian Institute of Technology, Bombay (IITB), India in 1999. From 2000 to 2001 he was at Bell Laboratories, Lucent Technologies, Murray Hill, NJ, USA. From 2002 he is with the Department of Electrical Engineering, IITB, where he is presently a Professor. He is also an Adjunct Professor of ECE Department at Purdue University. His research interests are electrical characterization of defects in dielectric-semiconductor interfaces; hot-carrier and bias temperature instability in CMOS devices; high-k and novel dielectrics for CMOS; and Flash EEPROMs. He has published more than 85 papers in refereed international journals and conferences, was invited to speak at several major international conferences including the IEDM, was a tutorial presenter at IRPS and has worked as a reviewer for many international journals and conferences. Dr. Mahapatra is an IEEE Electron Device Society Distinguished Lecturer.

 

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