3D Interconnect: Shaping Future Technology 2010 IEEE SCV-EDS/Applied Materials Technical Symposium January 29th, 2010 HYATT Regency 5101 Great America Parkway Santa Clara, CA 95054 Chair: IEEE SCV-EDS Prasad Chaparala
From	To	Session	Speaker
9:00 AM	9:30 AM	Registration
9:30 AM	9:45 AM	Opening Remarks	Prasad Chaparala, IEEE SCV-EDS
9:45 AM	10:15 AM	Taming Cost and Design Challenges for High Density Through Silicon Stacking (TSS)	Matt Nowak, Qualcomm
10:15 AM	10:45 AM	Modeling Thermo-Mechanical Stress Impact on Performance and Reliability of 3D Integration Structures	Xiaopeng Xu, Synopsys
10:45 AM	11:15 AM	Journey Toward Process Convergence in TSV Technology	Sesh Ramaswami, Applied Materials
11:15 AM	11:45 AM	3D FPGA - The Path to ASIC Density, Power, and Performance	Zvi Or-Bach, NuPGA
11:45 AM	1:00 PM	Lunch
1:00 PM	1:30 PM	A 3D-IC Technology with Integrated Microfluidic Cooling	Deepak C. Sekar, Sandisk
1:30 PM	2:00 PM	Technology Requirements and Standardization for 3D SiP	Arif Rahman, Xilinx
2:00 PM	2:30 PM	Advances in Copper Fill for 3D Interconnect Applications	Tom Ritzdorf, Semitool
2:30 PM	2:50 PM	Break
2:50 PM	3:20 PM	3D and More: A Renaissance in the Making	William Chen, ASE
3:20 PM	3:50 PM	3D Integration: The Evolution of Device Architecture, Packaging, and Manufacturing Infrastructure	Raj Pendse, STATS ChipPAC
3:50 PM	4:20 PM	Through Silicon Via (TSV) for 3D integration	C. Raman Kothandaraman, IBM
4:20 PM	4:50 PM	Q&A	All speakers
4:50 PM	5:00 PM	Closing Remarks	Prasad Chaparala, IEEE SCV-EDS
5:00 PM	6:30 PM	Reception / Poster Session