Upcoming Event: Tuesday April 23, 2019 (Note Date)


In-Package Optical I/O: Solving the Electrical I/O Bottleneck


Date: Tuesday, April 23, 2019 (N.B. not normal 1st Tuesday!!)

5:30pm: Networking/Light Dinner
6:30pm: Presentation
8:00pm: Adjourn

Location:

INTEL
Building SC-12
3600 Juliette Lane
Santa Clara, CA 95054

(Location: Take Montague Expy. OR Great America Exit off US 101; click to see instructions)

In order for chapter officers to estimate head count for food, Registration required! Register:

Title

In-Package Optical I/O: Solving the Electrical I/O Bottleneck

Speaker

Dr. Mark Wade, Ayar Labs

Abstract

Driven by relentless increases in high-performance ASICs (switches, GPUs, CPUs, DRAM, etc.), the electrical I/O roadmap is nearing its end, and the ASIC industry is looking for a ubiquitous replacement to electrical I/O escaping chip packages. To meet such demands, a photonics technology with massive bandwidth density, high energy efficiency, and low cost must be used. These requirements necessitate unprecedented levels of integration between electronics and photonics and require rethinking traditional communication architectures. In this talk, I will present a new class of commercial optical devices integrated directly into a high-volume 300mm 45nm SOI CMOS process and how these devices enable new SoC's to solve the bandwidth bottleneck in the ASIC industry.

Biography

Dr. Mark Wade:

Mark Wade is the President and Chief Scientist at Ayar Labs. He received his Ph.D. from University of Colorado Boulder in 2015. During his Ph.D., he was an NSF Graduate Research Fellow, a Visiting Researcher at MIT, and won the the 2015 College of Engineering and Applied Sciences Best Dissertation Award. In 2015, he was on the team that won the MIT Clean Energy Prize Grand Prize. In 2018, he received the PIC Conference Award for Advances in Photonics Integration for the work he and his team achieved at Ayar Labs. He is an author/co-author on over 50 peer-reviewed publications.