IEEE Magnetics Society
Santa Clara Valley Chapter


Thursday, April 5, 2018

Qualcomm, Inc. Building-B Cafeteria, 3165 Kifer Road, Santa Clara, CA 95051
Directions and Map
Check-in & Pizza at 6:15 P.M.- 6:45 P.M.
Presentation at
6:45 P.M. - 7:45 P.M.
Co-sponsored with
IEEE Santa Clara Valley Reliability Chapter



Machine-Learned Assessment and Prediction of Robust Solid State Storage System Reliability Physics

Dr.Jay Sarkar, Western Digital Corporation.




Reliability physics of the complex memory sub-system of modern, robust solid state storage devices (SSDs) under throughput acceleration stress can be analyzed leveraging Machine Learning – towards understanding their inherently designed fault-tolerance schemes that mitigate expected memory degradation mechanisms through their reliable warranty life as a system. Given the strength of multiple designed error-management schemes effectively countering multiple memory degradation mechanisms under stress, the developed empirical data based Machine Learning framework allows inferential and predictive assessments on reliable SSD design at system-level, in a quantitative and pro-active manner. Such Machine-Learned quantitative assessments on the system-level health of individual devices can be utilized towards assessing dynamic throughput stress impact on design, managing qualification reliability assessments and/or associated decision-making on the reliability of individual and populations of solid-state storage devices/systems. In this talk, the first published description of this research will be discussed, along with the context of independent research affirming the fundamental physics and related Machine Learning application on SSD device health.






Jay Sarkar is a Technologist at Western Digital Corporation focused on solid-state storage (SSD) analytics research and development. His prior professional experience has included core physics and reliability research and development on SSD technology, on the first Phase Change Memory technology implementation at Intel and Numonyx (Intel spin-off, now Micron) at 90 nm and 45 nm lithography nodes; and a novel reflective, power-efficient MEMS-based display technology development at Qualcomm. He has authored/co-authored 16 peer-reviewed international conference and journal papers across diverse domains of system and device physics, analytics, reliability and process modeling of SSDs, Phase Change Memory, 3-D NAND Flash memory and lower-dimensional electron transport. He has issued or filed/pending patents on machine-learned solid-state storage analytics, Phase Change memory array programming for robustness and MEMS encapsulation design. He earned a PhD in Electrical and Computer Engineering from the University of Texas at Austin (awarded the Ben Streetman Prize for dissertation research), M.S. in Applied Physics from Rice University, Houston and B.S. in Physics from the Indian Institute of Technology, Kharagpur. He is a member of the IEEE and has served on the Technical Program Committee of the International Reliability Physics Symposium (IRPS).

Slides will be uploaded later




!!! Tesla Factory Tour Raffle !!!

we may have the opportunity to get a Tesla Factory Tour! We will raffle off tickets (including waiting list). You must be a IEEE member and must be present to get on the list. We will need your name, IEEE membership number, title, company, and email address. Once we have a date and time from Tesla we’ll ask you to commit or de-commit to generate the final list. We will have 24 spots.!





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