IEEE Santa Clara Valley Reliability Chapter
Noel Tamayo, BSEE
Noel earned a B.S. in Electrical Engineering from Santa Clara University.
He has helped Fortune Global 500 companies improve fab yields by leveraging innovative inspection technologies, with key customer engagements at Intel, Samsung, IBM, and Toshiba.
He has 20 years of experience in semiconductor manufacturing, most recently as Senior Applications Engineer for Qcept Technologies, an equipment startup for non-visual inpsection, in Fremont, California. Prior to joining Qcept in 2008, he was the Applications Demo Lab Manager for the Macro Inspection group at KLA-Tencor. He has held previous positions in Photolithography and Etch Process Engineering at LSI Logic and IMP. His research interests include Photolithography, Semiconductor Yield Enhancement, and Customer Applications.
He has co-authored several papers for IEEE, ASMC, SPIE, and KLA-Tencor’s Yield Management Seminars.