IEEE Santa Clara Valley Reliability Chapter
Past Events (2015-2016)
|Thursday, December 1, 2016||Seminar||Reliability and Performance of Carbon Nanotube Vias||Dr. Cary Y. Yang||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Friday, November 11, 2016||Seminar||Device Circuit Interaction in Advanced Technology Nodes||Dr. William J. Dally, Dr. Victor Moroz, Dr. John Hu, Dr. Kevin Scoones, and Dr. Suresh Ramalingam||Texas Instruments, Bldg. E Auditorium, 2900 Semiconductor Drive, Santa Clara, CA, 95051|
|Thursday, November 3, 2016||Seminar||CPI stress induced carrier mobility shift in advanced silicon nodes||Dr. Valeriy Sukharev from Mentor Graphics Corporation||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Thursday, October 6, 2016||Seminar||Reliability and The Self-Driving Car||Mr. Noah Lassar from Goolge||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Thursday, September 1, 2016||Seminar||A Statistical FEA Method for Predicting Glass Fracture in Consumer Electronic Products||Dr. Marc Zampino from Amazon/Lab126||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Thursday, August 4, 2016||Seminar||Surfaces, Interfaces and Microelectronic Packaging||Dr. Guna Selvaduray From San Jose State Univeristy||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Wednesday, July 13, 2016||Seminar,Co-sponsored with The ASQ Silicon Valley Statistics and Reliability Discussion Group||Tesla Model S Battery, Charger, and Drive-Unit Reliability||Dr. Larry George||Applied Materials Bowers Cafe (aka Campus Cafe), 3090 Bowers Ave. Santa Clara, CA. 95054|
|Wednesday, May 11, 2016||Seminar,Co-sponsored with The ASQ Silicon Valley Statistics and Reliability Discussion Group||Taking practical steps towards Designing-for-Reliability||Mr. Georgios Sarakakis from TESLA Reliability Engineering||Applied Materials Bowers Cafe (aka Campus Cafe), 3090 Bowers Ave. Santa Clara, CA. 95054|
|Tuesday, April 12, 2016||Seminar, Co-sponsored by IEEE SCV Electronic Devices Society and Reliability Society||Learnings and insights from 52 years of Silicon Valley semiconductor experience||Ray Zinn, Founder and CEO of Micrel, San Jose, CA||Texas Instruments Building E Conference Center, 2900 Semiconductor Dr., Santa Clara, CA 95052.|
|Thursday, March 17th, 2016||Conference, Co-sponsored by Cisco Systems, Juniper Networks, and OPS Ala Carte||5th Annual IEEE International Reliability Innovations Conference||N/A||Juniper Networks , 1194 N Mathilda Ave, Sunnyvale, CA 94089 Building 1, Tuolumne Room|
|Thursday, March 3, 2016||Seminar||Physics based life distribution and reliability modeling of solid state drives||Dr. Alexander Parkhomovsky||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Saturday, January 30, 2016||One Day Course, co-sponsored by ASME SCV Chapter||Fracture Mechanics & Fatigue: Theory and Modeling for Mechanical Engineers||Dr. Metin Ozen, ASME Fellow, Principal, Ozen Engineering Inc, Sunnyvale, CA||Santa Clara University, 500 El Camino Real, Santa Clara, CA 95053|
|January 7th, 2016||Election||IEEE SCV REL Society 2016 Officers Election||N/A||Le Boulanger, 305 N Mathilda Ave, Sunnyvale, CA 94086|
|Dec 3rd, 2015||Seminar||Designed to Fail? Exploring Product Reliability Using JMP Pro||Laura A. Higgins, Ph.D, Sr. Systems Engineer, JMP, SAS Institute||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Nov 5th, 2015||Seminar||Software Reliability Best Practices||Nematollah Bidokhti, Principal Engineer at OCZ Storage Solutions||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Oct 1st, 2015||Seminar||Engineering the Right Accelerated Life Tests for Reliability Qualification||Sudarshan Rangaraj, Ph.D, Amazon Lab126 Reliability Manager||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Sept 3rd, 2015||Seminar, co-sponsored by the ASQ Statistics Group||Rethinking Failure Modes and Effects Analysis||John Flaig,Ph.D., Fellow of the American Society for Quality||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Aug 12th, 2015||Seminar by CPMT, co-sponsoring||Robust 3D-IC Package Assembly Process Engineering for High Volume Production||Inderjit Singh, Xilinx Inc.||Biltmore Hotel and Suites Santa Clara Hotel - 2151 Laurelwood Road Santa Clara, CA 95054|
|Aug 6th, 2015||Seminar||Macroscopic & Stochastic Aspects of Negative Bias Temperature Instability||Souvik Mahapatra, PhD, Professor of Electrical Engineering, Indian Institute of Tehnology Bombay, Mumbai, India||Texas Instruments, 2900 Semiconductor Dr. Santa Clara, CA, 95051|
|July 7th, 2015||Seminar||A New Drop Test for BGE Assemblies: Duplicable and Effective||Dongji Xie,Nvidia||Texas Instruments,2900 Semiconductor Dr. Santa Clara, CA, 95051|
|June 4th, 2015||Seminar||Adhesion and Thermomechanical Reliability for Emerging Device, Energy and Bio-Technologies||Prof. Reinhold H. Dauskardt,Professor of Materials Science & Engineering,Stanford University||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|May 7th, 2015||Seminar||Making Use of Reliability Statistics||Fred Schenkelberg, Consultant, FMS Reliability||Qualcomm Inc., 3165 Kifer Rd, Santa Clara, CA, 95051|
|Apr 2nd, 2015||Seminar, Cosponsored by IEEE SFBA MEMS & Sensors Chapter||Surface and Materials Engineering for Enhanced MEMS Reliability||Prof. Roya Maboudian, Dept of Chemical and Biomolecular Engg, UC Berkeley, CA||Atmel Corporation, 1600 Technology Drive, San Jose, CA 95110|
|Mar 5th, 2015||Seminar, Cosponsored by IEEE SCVCE||Reliability of Glass and Coatings||Stuart Douglas, Google [X] Reliability Engineer||Agilent Technologies, Santa Clara|
|Feb 5th, 2015||Seminar, Cosponsored by IEEE PSES and IEEE VTS||Tesla Reliability Challenges and Opportunities||Dr. Jiliang Zhang, Tesla Motors||Santa Clara University, Kennedy Commons|
|Jan 22nd, 2015||CPMT Event, Rel co-sponsored||Packaging Driven Reliability in High Voltage Packages.||Dr. Luu Nguyen||Texas Insturments, Inc Texas Instruments, Santa Clara|
|Jan 15th, 2015||Officers Meeting||Planning session||Officer Meeting||Agilent Technologies, Santa Clara|
|Date||Thursday, December 1, 2016|
|Topic||Reliability and Performance of Carbon Nanotube Vias|
|Abstract||As silicon integrated circuit (IC) technology node continues to scale down to the sub-10 nm regime, new structures and materials are required for front and back-end devices to keep up with the desirable IC performance and reliability. Currently, copper (Cu) and tungsten (W) are the industry-standard on-chip interconnect materials. However, aggressive scaling of interconnect linewidth leads to current density within interconnect lines fast approaching its bulk limit of ~1 MA/cm 2 , resulting in reliability problems due to electromigration. Thus, new materials with higher current-carrying capacities than Cu and W such as carbon nanotubes (CNTs) and graphene are needed. Although nanocarbons have electrical and mechanical properties superior to those of conventional metals, there are major challenges which must be overcome before they can be considered serious contenders to replace Cu and W as the interconnect materials in the end-of- roadmap regime. The singularly critical challenge for CNT via interconnects is optimizing carrier transport across the CNT-metal interface, or simply stated, minimizing the contact resistance. In an attempt to meet this challenge, we have fabricated via test structures down to 40 nm 40 nm using conventional silicon process technology, and grown vertically aligned CNT arrays inside these vias using plasma- enhanced chemical vapor deposition. Electrical measurements are performed using a nanoprober on individual vias with and without metallized via top contacts. Contact resistances for vias and individual CNTs are extracted from measured total resistances for various via and CNT heights, respectively. The results on CNT via resistance allow us to assess the via performance trend as linewidth decreases, and to project electrical performance for vias with widths 30 nm and smaller. Measured current capacities for 60 nm and 40 nm vias are two orders of magnitude higher than their Cu and W counterparts. However, both the measured and projected via resistances are still large compared with those of Cu and W vias with similar linewidths. Nevertheless, our scheme for contact engineering suggests that further innovations in contact improvement can lead to CNT via performance improvements, while preserving the superiority of high current-carrying capacity to all other potential replacements for Cu and W. Thus, a realistic assessment of CNT via interconnects for potential applications in end-of- roadmap IC technology nodes can then be achieved.|
|Date||Friday, November 11, 2016|
|Topic||Device Circuit Interaction in Advanced Technology Nodes|
|Abstract||This seminar will cover device, circuit and system/architecture level interactions and co-optimizations in advanced technology nodes.
This seminar consists of talks from five distinguished speakers below.
The first talk will examine the current state of the art in hardware for deep learning, and highlight the architecture and trends for system level hardware optimized for artificial intelligence applications. The following talk will expand into the device circuit interactions from finfet devices to devices for 5nm node and beyond. Standard cell layouts, variability, and performance power area co-optimizations will also be discussed. The 3rd talk will focus on the scaling challenges and process/design interactions, especially circuit and chip level performance, power, density, functionality/yield and reliability co-optimizations. Another important area to be addressed is the power devices and power management, which the 4th talk will focus on, covering the process needs of low voltage power management design and some of the key criteria to enable higher efficiency and lower cost. System level 3D integration will be the next important area to address the system level scaling requirements. The 5th topic will focus on the key advanced packing enabling technologies for 2.5D/3D and system level integrations.
|Date||Thursday, November 3, 2016|
|Topic||CPI stress induced carrier mobility shift in advanced silicon nodes|
|Abstract||Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing and detecting across-die out-of- spec stress-induced variations in MOSFET/FinFET electrical characteristics is addressed. A physics-based compact modeling methodology for multi-scale simulation of all contributing components of stress induced variability is described. A simulation flow that provides an interface between layout formats (GDS II, OASIS), and FEA-based package-scale tools, is developed. The EDA tool-prototype, developed on the basis of proposed methodology, can be used to optimize the floorplan for different circuits and packaging technologies, and/or for the final design signoff, for all stress induced phenomena. A calibration technique based on fitting to measured electrical characterization data is presented, along with correlation of the electrical characteristics to direct physical strain measurements. The limited characterization or measurement capabilities for 3-D IC stacks and a strict “good die” requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield.|
|Speaker||Dr. Valeriy Sukharev is a Technical Lead at the Design to Silicon Division (Calibre) of Mentor Graphics Corporation. He is a holder of the Ph.D. degree in physical chemistry from the Russian Academy of sciences. His major research activity is in development of new full-chip modeling and simulation capabilities for the EDA, semiconductor processing and reliability management. He has authored/co- authored more than 140 publications in scientific journals and conference proceedings and holds 20 plus U.S. patents. He has co-edited 2 books and co-authored one. He serves on the Editorial Boards and technical/steering committees of a number of profiling journals and conferences. He was a recipient of the 2014 Mahboob Khan Outstanding Industry Liaison/Associate Award (SRC).|
|Date||Thursday, October 6, 2016 (photos)|
|Topic||Reliability and The Self-Driving Car|
|Abstract||Since the automobile was invented over 100 years ago, engineers worked to make cars safer and more reliable. The 20th century witnessed continuous improvements in automotive reliability, coupled with a dramatic reduction in motor vehicle deaths per year. This was largely due to the development of stronger vehicles, active and passive safety systems, and comprehensive reliability development and test programs to weed out reliability and safety issues before they affected customers. At the same time, the driver --the most unreliable part of the car-- underwent no improvements. Given that 94% of traffic accidents involve human error, this is one place where we believe we really can really bring technology to bear. The self-driving car program is aimed squarely at replacing the human driver, and in doing so, making a step function improvement in automotive safety and reliability. Replacing a human driver comes with its share of reliability challenges. But by developing a self-driving vehicle from the ground up, and employing the best design for reliability and reliability test practices, we believe that we will soon live in a world where human-driven cars will seem like a relic of the 20th century.|
|Speaker||Noah Lassar is the Senior Manager of Reliability for the Google[X] Self-Driving Car. Noah also acts as an advisor to Alta Motors, developer of high performance electric motorcycles. Prior to joining Google[X], Noah worked as the Manager of Reliability at Tesla Motors, where he developed and executed the reliability program for Tesla's Model S and the Toyota Rav4 EV. Noah received his Master's degree in Mechanical Engineering from Stanford University in 2004. When Noah is not working on reliability challenges, he enjoys exploring the world with his wife and two children.|
|Date||Thursday, September 1, 2016 (photos)|
|Topic||A Statistical FEA Method for Predicting Glass Fracture in Consumer Electronic Products(slides)|
|Abstract||A critical risk assessment for handheld consumer electronic products is the probability of fracture for glass components, namely the display system, during drop impact. Glass strength can be determined through four point bend testing and combined with product level (FEA) simulations for multiple drop orientations, producing a temporal and spatially varying stress state on the glass. The simplified technique of using only peak values in the worst orientations is generally over-conservative and not effective for competitive design where reliability must be balanced with cost, weight and industrial design requirements. Evaluating the probability of failure for this class of problem is not trivial and poses several challenges for the analyst. In this presentation, these challenges will be discussed with potential solutions methods to show that an effective risk assessment method is possible which uses the FEA data directly, addressing the size and rate effects on glass strength, the temporal and spatial nature of the stress results, and the combining of drop orientations to produce a probability of failure which is demonstrated to have excellent correlation with multiple product test cases using both EPD and LCD systems.|
|Speaker||Marc Zampino is currently a Senior Design Analysis Engineer at Amazon/Lab126, as part of the Product Integrity organization, joining Amazon in 2011. He brings over thirty years of experience as a mechanical engineer developing products in both the consumer and military electronic sectors, providing expertise in thermal, structural, and fluid simulations and analysis, product design and testing, materials testing, and failure analysis and mitigation. Prior to Amazon, he was a Principal Staff engineer at Motorola and Foxconn focusing on structural and thermal analysis of cellular phone products, with a focus on the reliability of the glass components in drop impact, including the characterization and testing of glass, the prediction of glass failure, and the meaningful specification of glass strength. He holds a Ph.D. in Mechanical Engineering from Florida International University and later became a faculty member there for over five years, teaching and doing research in the structural integrity and advanced thermal management of High and Low Temperature Cofired Ceramic systems. He successfully fabricated miniature/micro scale heat pipes and spray cooling systems, pulsatile pumping loops, and micro-furnace structures, all integrated internally into the ceramic substrate for various DARPA and industrial clients and generated 22 referred papers.|
|Date||Thursday, August 4, 2016 (photo)|
|Topic||Surfaces, Interfaces and Microelectronic Packaging (slides)|
|Abstract||Of the total cost involved in producing a microelectronic component, between 50% to 90% goes towards the packaging, depending on the specific type of die and packaging technology. However, approximately 95% of the reliability issues are actually related to the packaging rather than the die. There are a variety of surfaces and interfaces, the integrity of which needs to be maintained at all times, in order for the die to be able to function reliably over its service life. Some of these surfaces and interfaces are obvious while others are not. The integrity of these surfaces can have a major impact on the long term reliability of the packaged die. The detailed composition of the interface can also change over time. This presentation will focus on a discussion of the interfacial interactions between Pb-free solders and substrates, the nature of these interactions, the intermetallic compounds (IMC) that are formed, and how these interaction layers can change over time.|
Dr. Guna Selvaduray joined San Jose State University in Fall 1984. He obtained his M.S. and Ph.D. degrees in Materials Science & Engineering from Stanford University, and his B. Eng. Degree in Mechanical Engineering from Tokyo Institute of Technology. His current research interests include microelectronic encapsulation and interconnect issues, issues related to Pb-free solders for microelectronics, materials issues related to biomedical implants, corrosion and surface phenomena, and environmental issues related to engineering materials.
He has been involved in microelectronic packaging education and research for more than 25 years, including the creation of a graduate level curriculum at San Jose State University. One of his current efforts is focused on exploring issues concerning microelectronic packaging for biomedical devices, especially implants - an industry sector that holds great promise for the future. The International Microelectronics and Packaging Society recognized his efforts by awarding him its Outstanding Educator Award in 2008.
His research and scholarly activities have attracted funding from a variety of government agencies and private companies. He has supervised approximately 120 M.S. theses and B.S. senior projects. He has over 100 publications and has made over 120 technical presentations. Guna is also a consultant to industries in the USA and Japan. An avid international traveler who enjoys the diversity this brings to him, Guna speaks five languages including Japanese.
|Date||Wednesday, July 13, 2016|
|Topic||Tesla Model S Battery, Charger, and Drive-Unit Reliability|
http://www.pluginamerica.org surveys electric car owners. I used their Tesla Model S battery, charger, and drive-unit data for nonparametric estimates of reliability, including bivariate, for our education:
Nonparametric, multivariate reliability analyses can be done, without unwarranted assumptions, without life data, and with dependence and censored data. Using R, max. likelihood, least squares, and max. entropy. Biostatisticians do it, with life data.
Conclusions and recommendations:
Progress in Artificial Stupidity:
Georgios Sarakakis is a Senior Manager of Reliability Engineering at Tesla Motors. He has overseen the reliability development and continuous improvement for the Tesla Roadster, Model S and Model X. As a founding member of the reliability staff at Tesla, he has scaled the team to a world-class organization that drives innovation on multiple fronts, from a data-driven and physics of failure-based approach in Design for Reliability to pairing big data with classical reliability techniques. Prior to joining Tesla, Georgios worked as a Research Scientist at ReliaSoft, where he consulted with various industries, and as a Reliability Engineer at HP, where he worked on the reliability development and launch of the Page Wide Array inkjet technology.
Georgios is an author of numerous published papers and articles in the areas of reliability engineering and management. He is a sought-after speaker in the area of product reliability management and strategy. His presentations at ARS have been voted at 1st place in 2013 and 2014 and 2nd place in 2015. In 2014, he won the ASQ Brumbaugh Award for co-authoring the paper that made the largest contribution in the industrial application of quality improvement.
Georgios holds an MS in Reliability Engineering from the University of Arizona and an MS in Project Management from George Washington University's School of Business. He is certified as a Project Management Professional, Reliability Engineer, Reliability Professional and Six Sigma Black Belt.
|Date||Wednesday, May 11, 2016|
|Topic||Taking practical steps towards Designing-for-Reliability|
|Abstract||Design-for-Reliability sounds like a great concept and it has become a common catchphrase across various industries. But what does it really encompass and how do you enable this to happen in an organization? This presentation will provide a detailed insight on the elements of designing-in reliability and what the practical steps are that organizations can take to start moving towards that direction. We call that " swimming upstream " as organizations move from a reactive culture in reliability to a more proactive one, where problems are identified and addressed upstream in the product development process instead of being detected in late testing or in the field.|
|Speaker||Dr. Larry George is not a Tesla employee he does reliability statistics, for free. He tries to change reliability practice to use field reliability, what really happens. He has PhD in Industrial Engineering and Operations Research from UC Berkeley with minor in statistics. He taught for 11 years , worked for Lawrence Livermore National Labs for 11 years, and has worked in the real world for almost 30 years. He is a member ASA Statistics Without Borders, INFORMS, ASQ CRE and Fellow. Industrial strength speaker for ASA, INFORMS, AAAS.|
|Date||Tuesday, April 12, 2016|
|Topic||Learnings and insights from 52 years of Silicon Valley semiconductor experience|
|Abstract||Ray Zinn is the history of the Silicon Valley semiconductor industry. With 50 years in the business, having founded Micrel and leading it for 37 years, Zinn has seen the industry grow, crash and undulate through repeated business cycles. Yet Zinn′s company remained profitable for 36 of its 37 years. Zinn′s talk to the IEEE Electron Devices group will be about the past and the future. He′ll discuss the history of the industry and of Silicon Valley, from his time at Fairchild through today. Zinn will relate why some companies thrived, some got lucky and others faded into oblivion. Zinn will also offer some insight into why this history helps predict the current industry consolidation cycle and where it is heading next.|
|Speaker||Raymond D. ″Ray″ Zinn is an inventor, entrepreneur, and the longest serving CEO of a publicly traded company in Silicon Valley. He is best known for creating and selling the first Wafer Stepper (an industry standard piece of semiconductor manufacturing equipment), and for co-founding semiconductor company, Micrel (acquired by Microchip in 2015), which provides essential components for smartphones, consumer electronics and enterprise networks. He served as Chief Executive Officer, Chairman of its Board of Directors and President since Micrel′s inception in 1978 until his retirement in August 2015. Zinn′s philosophy on people, servant leadership, humanistic management and the ethics of corporate culture are credited with Micrel′s nearly unbroken profitability. Zinn also holds over 20 patents for semiconductor design. A proud great-grandfather, he is actively-retired and mentoring entrepreneurs. His new book, Tough Things First (McGraw Hill), is available at ToughThingsFirst.com, Amazon and other fine booksellers. In addition, review copies are available upon request.|
|Date||Thursday, March 17, 2016|
|Topic||5th Annual IEEE International Reliability Innovations Conference|
|Date||Thursday, March 3, 2016|
|Topic||Physics based life distribution and reliability modeling of solid state drives|
|Abstract||The model of solid state drive (SSD) life time distribution from physics-based life model considering the random nature of real world customer data usage and product inherent physical properties is developed. The talk is focused on the following two cases: Case 1: When only field write duty cycle is treated as a random variable while assuming all other physical characteristics are non-random, it is found that the SSD life time follows . Reciprocal-Weibull distribution when field Write Duty Cycle follows Weibull distribution, . Reciprocal-Exponential distribution when field Write Duty Cycle follows Exponential distribution, . Lognormal distribution when field Write Duty Cycle follows Lognormal distribution, . Reciprocal-Normal Distribution when field Write Duty Cycle follows Normal distribution. The corresponding mathematical expressions for reliability, unreliability, hazard rate, MTTF, etc. are derived for each scenario accordingly. Case 2: In real world, SSD endurance rating is also a random variable due to part-to-part variance from material in-homogeneity and inherent defects from manufacturing process. Given the distributions of field customer write duty cycle (stress) and SSD endurance rating (strength), the distribution of lifetime random variable can be derived either analytically, if closed form solution exists, or numerically using Monte Carlo simulation if no closed form solution exists. This paper provides a special case where the analytic solution exists when both random variables follow Lognormal distribution. A numerical example is given to show the application of the models developed in this paper. The results derived in this paper will benefit the SSD industry in various aspects of product design, development, reliability testing and prediction, field return/failure estimation and warranty management.|
Alexander Parkhomovsky, Ph.D. is an expert in physics of failure and design for reliability. Dr. Parkhomovsky developed and implemented a number of disruptive test and modeling solutions in optics, semiconductor microelectronics and mechanics. Alexander Parkhomovsky has a broad industry expertise and experience working with technology leaders such as Lumentum, JDSU, Seagate Technology , Western Digital, Space Systems/Loral and Applied Materials where he developed and patented a number of industry leading models and tests to optimize product reliability.
During his career Alexander Parkhomovsky was awarded by the Outstanding Technical Contributions Awards by Seagate Technology. He has been selected by the National Academy of Engineering along with the 100 top young engineering leaders from Government, Industry and Academia to participate in the Frontiers of Engineering Symposiums.
Alexander Parkhomovsky authored and co-authored numerous scientific publications. He is a co-inventor on 4 U.S. Patents.
Dr. Parkhomovsky received his Ph.D. degree in Materials Science from the University of Minnesota and his B.S. and M.S. in Chemical Engineering degrees from Mendeleyev University of Chemical Technology, Moscow, Russia.
|Date||January 30, 2016|
|Topic||Fracture Mechanics & Fatigue: Theory and Modeling for Mechanical Engineers|
|Abstract||This course covers detailed information on the Fracture Mechanics and Fatigue theory as well as numerical modeling. The course reviews the fundamentals of fracture mechanics and fatigue; history, derivation of mathematical expressions for stress intensity factors; 2D versus 3D, crack tip stress field, three modes of fracture, maximum principal stress criterion, crack initiation and crack propagation, strain energy density theorem, J-Integral, mixed mode cracking, XFEM method, cohesive zone modeling, implementation of crack modeling in ANSYS Workbench, fatigue crack growth, stress/strain/energy based fatigue, numerical modeling of fatigue. Attendees will receive instructions to download free 30 days ANSYS/Mechanical software license at the end of the seminar (restrictions apply)*. Attendees will not need either the software installed on their system or experience with ANSYS to attend the seminar. Software can be downloaded after the seminar to practice the workshop problems demonstrated during the course.|
|Speaker||Metin Ozen, Ph.D. is currently operating a high technology consulting firm, Ozen Engineering Inc., performing advanced multi-physics Finite Element Analysis (FEA) and Computational Fluid Dynamics (CFD) simulations for his clients and is an ANSYS Channel Partner. He is a leader in Silicon Valley in applying simulation technology. Dr. Metin Ozen received BS Mechanical Engineering and MS Applied Mechanics degrees from Lehigh University and a PhD from University of Connecticut in Applied Mechanics. He is an ASME Fellow, honored for his contributions to Mechanical Engineering. He states, ″I′m passionate about FEA and CFD simulation solutions and am dedicated to continuously advancing the study and practice of computer-aided engineering.″ Dr. Metin Ozen brings with him over 30 years of experience in Applied Mechanics. He has provided key technical support, training, and consulting work for ANSYS software in the Bay Area. He has taught classes throughout the country on topics such as MEMS, Fracture Mechanics and Fatigue, Ball Grid Arrays (BGAs), Heat Transfer, Dynamics, CFD, Electromagnetics, and Finite Element Methods. In 2001-2002, Dr. Ozen served as the Chair of the Silicon Valley Chapter of ASME. Metin′s personal interests include tennis, soccer, and archaeology.|
|Date||January 7, 2016|
|Date||Dec 3, 2015|
|Topic||Designed to Fail? Exploring Product Reliability Using JMP Pro|
|Abstract||Product reliability is strongly tied to business success and perception of quality. Product design can greatly influence the overall reliability of a product. Uncovering vulnerable components inside a system and accurately making predictions on both individual components and complete systems is challenging. Not considering alternative designs or failing to identify latent weaknesses can result in catastrophic and unexpected failures. Early design phase implementation of reliability block diagrams turns design alternatives into quantitative decisions before problems occur. I will show how evaluating reliability block diagrams in JMP Pro can both compare designs and find vulnerabilities inside systems.|
|Speaker||Laura Higgins, Ph.D. is a JMP Sr. Systems Engineer who is based in San Francisco. Working with JMP customers, she helps users understand how to quickly find the value in their data using JMP.|
|Date||Nov 5th, 2015|
|Topic||Software Reliability Best Practices|
|Abstract||The intent of the talk is to introduce the Software Reliability Engineering (SRE) as an established discipline and highlight elements from the new IEEE standard on software reliability best practices that will be published soon. This is an advanced look into what the new standard will discuss. These recommended best practices are a composite of models, analyses and processes that describe the ″what and how″ of SRE. It is important for an organization to have a disciplined process if it is to produce high reliability software. These recommended practices present a life-cycle approach to SRE that may be used with phased, incremental, or evolutionary development. The applicability and use of these recommended practices to hardware reliability engineering will also discussed.|
|Speaker||Nematollah Bidokhti is a Principal Engineer at OCZ Storage Solutions and a senior member of IEEE. Nematollah has worked in many industries and markets such as consumer, enterprise, service provider and defense. He has worked in areas such as Cloud, Networking, Computing, Storage, MEMS and Optical. Nematollah has contributed to many conferences as an author, moderator, keynote and organizer. His areas of research are cloud & SW reliability, system fault tolerance and reliability automation.|
|Date||Oct 1st, 2015|
|Topic||Engineering the Right Accelerated Life Tests for Reliability Qualification|
|Abstract||Various reliability testing standards like JEDEC/AED/MIL/IEC etc. are commonly used in the semi-conductor and consumer electronics for reliability qualification of IC components and consumer electronics devices. However, ″blanket″ qualification criteria that are not based on knowledge of customers′ usage behaviors and physics of failure expose the manufacturers to two risks. At one end of the spectrum lies the risk of over-design and added cost while on the other end lie the risks of field failures, warranty costs, negative user experience and erosion of the corporation′s brand. The present talk will draw upon examples from semi-conductor chip/package and consumer electronics to compare qualification criteria based on standards to those based upon product use conditions. Widely prevalent failure modes like moisture diffusion in polymers and fatigue of solders will be invoked to make quantitative comparisons between standards and use conditions based reliability qualification criteria. The talk will take a critical look at JEDEC criteria for temperature-humidity, thermal cycling and bake testing.|
|Speaker||Sudarshan Rangaraj is a hardware reliability manager at Amazon Lab126 working on reliability of a variety of IoT devices and Accessories. Prior to Amazon, Sudarshan worked at Intel corporation as a Thermo-Mechanical Reliability group leader in the Technology and Manufacturing Group. During his 11 years at Intel, Sudarshan worked on chip-package interaction reliability, IC packaging, thermo-mechanical simulations and mechanical design of sockets/connectors. He holds a Ph.D. from Purdue University specializing in Mechanics of Materials. He has co-authored over 25 journal and conference publications and holds 8 patents.|
|Date||Sept 3rd, 2015|
|Topic||Rethinking Failure Mode and Effects Analysis|
|Abstract||The classic version of FMEA is an engineering tool for quality and reliability improvement through project prioritization. It was formally released by the U.S. government with MIL-P-1629 in 1949 and updated in 1980 as MIL-STD-1629A. The classic FMEA methodology has proven to be reasonably effective tool for product, service, and process improvement over the years, but it′s by no means optimal.
Each part of the system, subsystem, or component is analyzed for potential failure modes, possible causes, and the possible effects. The possible failure mode is given a rank score from 1 to 10 in three categories: severity, occurrence, and detection. Multiplying these three category ranks together will yield a number called the risk priority number, or RPN, which is between 1 and 1,000. The RPN results are reviewed for each failure mode, and corrective action projects are prioritized based on the RPN (i.e., the higher the RPN, the higher the corrective action priority). We will explore some of the deficiencies in classic FMEA to see where improvements might be made.
|Speaker||John J. Flaig, Ph.D., is a fellow of the American Society for Quality and is managing director of Applied Technology at www.e-at-usa.com, a training and consulting company. Flaig has given lectures and seminars in Europe, Asia, and throughout the United States. His special interests are in statistical process control, process capability analysis, supplier management, design of experiments, and process optimization. He was formerly a member of the Editorial Board of Quality Engineering, a journal of the ASQ, and associate editor of Quality Technology and Quantitative Management, a journal of the International Chinese Association of Quantitative Management.|
|Date||Aug 12th, 2015|
|Topic||Robust 3D-IC Package Assembly Process Engineering for High Volume Production|
|Abstract||As the size and complexity of designs grows larger, Field Programmable Gate Array (FPGA) based design solutions are becoming more dominant in system designs due to their ability to offer higher logic capacity and more on-chip resources. FPGA-based design solutions that offer higher capacity and higher bandwidth with low latency and power can provide system-level functionality similar to Application Specific Integrated Circuits (ASICs). Stacked-die technology enables high-bandwidth connectivity between the multiple die by providing a significantly large number of connections via microbumps. This interposer-based die stacking approach provides low power and latency, but also adds manufacturing complexity. This talk will summarize some of the key assembly and reliability challenges of 28nm 3DIC products assembled with CoWoS (Chip-On-Wafer-On-Substrate) process. During the initial product ramp stage, most of the failures observed were related to interposer-level assembly processes. Specific patterns were developed to isolate the interconnect failures to single ubumps. Apart from interconnect failures, transistor damage occurred during the 3DIC assembly process causing functional failures which were investigated, analyzed and resolved to demonstrate a high-yielding 3DIC assembly process. To understand the reliability of the 3DIC device, a comprehensive reliability test vehicle was developed. The reliability of the 3DIC device mounted on the board was tested for various high temperature storage and thermal cycling test conditions far beyond JEDEC requirements. The comprehensive test methodology was effective in capturing various failure modes and their interactions. During this presentation an overview of the initial development process, reliability data, and key challenges will be discussed.|
|Speaker||Inderjit Singh received his Bachelor of Applied Science, majoring in Applied Physics from University Science Malaysia. He has 25 years of Assembly, Manufacturing, Package Development, Design, Reliability & Chip to Package interaction experiences. His focus areas have been in the development of interconnect technologies & considered an industry expert related to Wirebonding, Flip Chip & 3D packaging. He previously worked at National Semiconductor & NVIDIA for 10 years each & currently been with Xilinx for the last 5 years as Director of Assembly Engineering, managing Overall Package Assembly and Process Integration & New Product/Package ramping to production.|
|Date||Aug 6th, 2015|
|Topic||Macroscopic & Stochastic Aspects of Negative Bias Temperature Instability|
|Abstract||Negative Bias Temperature Instability (NBTI) is a crucial reliability concern for modern day state-of-the-art CMOS technologies. NBTI results in shift in MOSFET parameters, such as threshold voltage, drain current, etc., over time, and therefore causes long-time failure of CMOS integrated circuits. It is very important to understand the fundamental physical mechanism responsible for NBTI and develop suitable models to predict device and resultant circuit degradation at end product life.
In this talk, the underlying physical processes responsible for NBTI in High-K Metal Gate (HKMG) MOSFETs will be briefly reviewed. Defect generation in MOSFET gate oxide will be explained from both macroscopic and stochastic viewpoints, which will be respectively useful to explain NBTI degradation in large and small area devices. This novel simulation framework can explain DC and AC NBTI degradation under various operating conditions such as different operating voltage, temperature, frequency and duty cycle in large area devices, as well as NBTI variability in small area devices. Furthermore, a compact model will be developed to simulate NBTI induced circuit degradation using SPICE simulation, and specific example of variable NBTI impact on SRAM performance parameters, such as read and hold static noise margin and write access time will be discussed.
|Speaker||Souvik Mahapatra received his PhD in Electrical Engineering from IIT Bombay, Mumbai, India in 1999. During 2000-01, he was with Bell Labs, Lucent Technolgies, Murray Hill, NJ, USA. Since 2002 he is with the Department of Electrical Engineering at IIT Bombay and currently holds the position of full professor. His current research interests are in the area of CMOS logic gate stacks - scaling and reliability.
He has published more than 150 papers in peer reviewed journals and conferences, delivered invited talks and tutorials in major international conferences including at the IEEE IEDM and IEEE IRPS, and served as a committee member and session chair in several IEEE conferences. He is a fellow of the Indian National Academy of Engineering, senior member of IEEE and a distinguished lecturer of IEEE EDS.
|Date||July 7th, 2015|
|Topic||A New Drop Test for BGA Assemblies: Duplicable and Effective|
|Abstract||The drop test per JEDEC standard (JESD22B111) has been widely used for evaluating the mechanical reliability of solder joints of BGAs for more than a decade. In JESD22B111, a rectangular board, 3"x5", with 15 BGAs has been employed as the test vehicle (TV). Because those 15 components have to be divided into 6 subgroups according to their stress levels, this requires a large sample size and a large number of drops in order to get statistically meaningful results. Due to the nature of the drop test, the variation of drop cycles to failure is normally much greater than other types of fatigue test such as bending and thermal cycling. This makes the current drop-test method very ineffective and inefficient. A second shortcoming for this standard is that only two parameters -- acceleration and drop duration -- have been defined, which may be not sufficient. Some experimental studies demonstrated that number of drops to failure would be significantly different for the same units but tested in two test labs even though they are tested using the same drop test parameters. The gap is even larger if using different drop testers. That is because the drop test setup is controlled not only by the peak acceleration and shock duration but also by the pulse shape and energy consumption.
To solve the non-uniformity issue using rectangular boards per JESD22B111, a new TV using 3"x3" and 1mm thick is proposed, and assembled using a 12x12mm2 BGA package. In this TV, 4 BGAs are mounted orthogonally with the same distance to the board center so that all inner and outer corner solder joints of all 4 BGAs are at the same stress level respectively during the drop test. To validate the stress level, PCBs on both rectangular (3"x5") and square board (3"x3") are designed in the same way in terms of BGA component, pad stackup, pad structure and fabricated by the same workshop. To understand the repeatability, the drop tests were repeated in four (4) different test labs. Those test labs belong to different companies and may use different drop testers. But they all use the same drop test parameters (1500G, 1ms).
The drop test includes two key items: strain measurement and drop cycle to failure. The PCBs with several strain gage attachments were measured for both TVs and repeated for each test lab. Interestingly enough, it is found that the strain values are comparable to each other among the four test labs but the number of drops to failure is spread very differently. This give us a big alarm that drop test results should be interpreted carefully. Further analysis shows that another parameter, energy dissipation or delta V during the drop cycle, plays a key role but has been neglected by the current JEDEC drop test standard. This study has demonstrated that the drop duration is far less critical as compared to the peak acceleration and delta V for defining the damage of the solder joints. To further understand the shape impact of the acceleration pulse, a spectrum response has been analyzed which proves only the peak acceleration and delta V may be considered to determine the severity of a drop test.
This is a part of JEDEC B111 Task Group work. The participant companies are (in alphabetical order) Aalto University, Amkor, Auburn University, Blackberry, Cisco, Flextronics, Freescale, Hewlett-Packard, Huawei Technologies, Intel, Lamar University, Maxim Integrated, Microsoft, NVIDIA, Qualcomm, Texas Instruments.
|Speaker||Dongji Xie is currently working in NVIDIA in Santa Clara as senior manager for system reliability. He has been working in reliability and manufacturing in the electronics industry from wafer processing, packaging, PCB assembly for more than 20 years. He received his Ph.D. from City University of Hong Kong and Bachelor and Master Degrees both from Huazhong University of Science and Technology, China. He has been a committee member for Applied Reliability of ECTC since 2002.|
|Date||June 4th, 2015|
|Topic||Adhesion and Thermomechanical Reliability for Emerging Device, Energy and Bio-Technologies|
|Abstract||Material layers and interfaces in emerging device packaging and flexible electronic technologies operate near the envelope of their mechanical and adhesive properties with remarkably high levels of film stress. Debonding and cohesive fracture are major challenges for device reliability at all levels of processing, packaging and service. The thermomechanical properties of device structures including complex back-end interconnect, emerging 3-D packages, and flexible organic electronic structures are critical for aiding new materials integration as well as understanding device reliability.
We describe research aimed at characterizing thin-film thermomechanical properties including adhesion and cohesion that are critical for such emerging device technologies. We focus on hybrid films comprising inorganic and organic components tailored at molecular length scales used in applications ranging from protective transparent coatings in flexible display and photovoltaic devices, membranes in fuel cells, interlayer dielectrics in microelectronics, adhesive layers in high-performance laminates, and layers in flexible organic electronics and photovoltaics. Reliability integrating new multi-functional hybrid films requires a new understanding of their mechanical properties, how to characterize them, and how they are related to underlying molecular structure. We describe our research by showcasing several examples in these application areas.
We finally consider how fabrication or operating environments may affect device reliability. We will particularly consider the synergistic effects of environmental species like moisture, mechanical stresses, and temperature on the kinetic processes of damage formation and growth. These are central to understanding and predicting device reliability through processing and service.
|Speaker||Dr. Reinhold H. Dauskardt is the Ruth G. and William K. Bowes Professor in the Department of Materials Science and Engineering with additional appointments in Mechanical Engineering, the Biodesign Institute and the Department of Surgery. His research group works on integrating new materials into emerging device and energy technologies and on the biomechanics and regenerative processes of human skin and soft tissues. He is an internationally recognized expert on the thermo-mechanial reliability of device technologies and has pioneered quantitative methods for adhesion and cohesion characterization in thin-film structures. Experimental studies are complimented with computational and modeling simulations. He has received numerous awards including the Maso Award for fundamental contributions to skin science (2011), the IBM University Research Award in recognition of scientific and technological research achievements (2011), the Semiconductor Industry Association University Researcher Award for research which has provided substantive and sustained contributions to semiconductor industry science and technology (2010), an IBM Faculty Award (2006), the ASM International Silver Medal (2003), an Alexander von Humboldt Research Award (2002) and the U.S. Department of Energy Outstanding Scientific Accomplishment Award (1989). He is a Fellow of the American Ceramics Society (2008) and the ASM International (2010). His interdisciplinary research includes interaction with researchers in academia, industry, and clinical practice. He has published over 300 articles in the scientific literature.|
|Date||May 7th, 2015|
|Topic||Making Use of Reliability Statistics|
|Abstract||Mastering the statistical tools related to reliability engineering allows you to master reliability. Identify, characterize, understand, predict, and improve reliability all require statistics. Let′s discuss how it works and will work for you.
Variability causes failures. From the variability of material properties to use conditions all lead to the uncertainty of when and what will fail. Statistics is the language of variability. Given nearly everyone truly enjoyed their undergraduate probability and statistics course, let′s start the discussion on essential elements of reliability statistics.
Understanding when something will likely fail provide real value to the design team and the business and the customer. We don′t use statistics just because it′s cool (which it is, btw), we use statistics to reveal problems, to characterize variability, and to make decisions. We use statistics to create reliable products. Let′s review a couple of case studies where reliability statistics made the difference.
Let′s explore maintenance planning for a fleet of escalators. Then let′s examine a medical product field data and help the team focus on specific areas to improve the system′s reliability. We′ll finish the discussion with a short discussion on the next steps to get started when confronted with some data. Let′s find the motivation to use reliability statistics, plus find the resources to learn the statistical tools necessary to be successful.
|Speaker||Fred Schenkelberg is an international authority on reliability engineering. He is the reliability expert at FMS Reliability, a reliability engineering and management consulting firm he founded in 2004. Fred left Hewlett Packard (HP)′s Reliability Team where he helped create a culture of reliability across the corporation to assist other organizations. His passion is working with teams to improve product reliability, customer satisfaction, and efficiencies in product development; and to reduce product risk and warranty costs. Fred′s areas of expertise are: reliability program development, accelerated life test design and analysis, reliability statistics, risk assessment, test planning, and training. He has a Bachelor of Science in Physics from the United States Military Academy and a Master of Science in Statistics from Stanford University.|
|Date||Apr 2nd, 2015|
|Topic||Surface Materials Engineering for Enhanced MEMS Reliability|
|Abstract||Advances in the micro- and nanoelectromechanical systems (M/NEMS) have created a growing interest in evaluating the reliability of these miniaturized devices. The critical reliability issues include adhesion (also called stiction), friction, wear and corrosion. In this presentation, the impact of these interactions in the M/NEMS technology will be discussed. I will also introduce a number of MEMS-based microinstruments that we have developed to study these interactions, the insights we have gained using them about the nature of surface interactions involved in M/NEMS, and some of the solutions we have developed to address them.
Silicon has been the dominant semiconducting material in micro-/nanosystems technologies. However, the material and surface properties of silicon impose limitations on its use in applications involving harsh environment (such as high temperature, high radiation and corrosive conditions). Silicon carbide (SiC), a wide bandgap semiconductor, is emerging as a material to address the limitations of silicon as it is temperature tolerant, radiation resistant, and chemically inert. In the second part of my talk, I will present recent advances, by our group and others, in the materials science and manufacturing technology of SiC MEMS, with particular emphasis on sensor and energy technologies.
|Speaker||Roya Maboudian is Professor of Chemical and Biomolecular Engineering and Co-Director of the Berkeley Sensor & Actuator Center at the University of California, Berkeley. She is currently serving as editor to the IEEE Journal of Microelectromechanical Systems (JMEMS), and as associate editor to IEEE/SPIE Journal on Micro/Nanolithography, MEMS and MOEMS (JM3).
Prof. Maboudian received her B.S. degree in Electrical Engineering from the Catholic University of America, Washington, D.C., and her M.S. and Ph.D. degrees in Applied Physics from the California Institute of Technology in Pasadena. Her research interest is in the surface/interface and materials science and engineering of micro/nanosystems, with applications in harsh-environment sensing, health and environmental monitoring, and energy technologies. She is the recipient of several awards, including the Presidential Early Career Award for Scientists and Engineers (PECASE) from the White House, NSF Young Investigator award, and the Beckman Young Investigator award. She is a Fellow of the American Vacuum Society.
See also: http://cheme.berkeley.edu/people/faculty/maboudian
|Date||Mar 5th, 2015|
|Topic||Reliability of Glass and Coatings|
|Abstract||For consumer electronics companies building tablets, phones, and laptops, glass fracture is often a cause for customer returns, replacements, or dissatisfaction. This presentation will review basic fracture mechanics, types of glass used in consumer electronics, and ways to quantify the material reliability. A methodology to use material data to quantify reliability at the system level will be provided. In addition, a brief overview of typical glass coatings and ways to test their reliability will be presented.|
|Speaker||Stuart Douglas is a Reliability Engineer at Google [X] working on special projects. He has supported projects such as the Chrome, Self Driving Car, Glass, and Makani. Before joining Google, he worked on several generations of Kindle E-readers and Tablets and led analysis into the reliability of glass displays at Amazon and Lab126. Stuart's research includes test and analysis of MEMS and electronics packages, brittle materials and thin films, and large mechanical systems. His academic research has been featured in two keynote IEEE EuroSimE conferences and won a "Best Thesis" university award. Stuart has a B.S. in Aerospace and a M.S. in Mechanical Engineering from University of Maryland at The Center for Advanced Life Cycle Engineering.|
|Date||Feb 5th, 2015|
|Topic||Tesla Reliability Challenges and Opportunities|
|Abstract||There are serious challenges to Tesla vehicle reliability in term of required reliability, short product development cycle, complexity of the product, number of suppliers, etc. In addition, there are tremendous opportunities at Tesla in terms of reliability emphasis, business model uniqueness, data/statistics driven culture, technology and process innovation etc. Tesla′s goal is to build up a unique reliability program that takes the advantages of both traditional automotive reliability and high tech reliability. This presentation focuses on Tesla unique automotive OEM reliability program development. Our innovative approaches in reliability goal setting and allocation, prior knowledge utilization, distributional usage based accelerated reliability test design, field reliability evaluation, etc. Future directions in Tesla reliability program will also be discussed.|
|Speaker||Dr. Jiliang Zhang is a Staff Reliability Engineer at Tesla Motors. He has more than 15 years of reliability and quality professional experience in printer, consumer electronics, and automotive industries. Dr. Zhang′s experience includes reliability program development, reliability test design, test and field data analysis as well as Design-for-Reliability. He has worked for Hewlett-Packard Co. and Amazon Kindle Hardware in product reliability and product quality. He received his Ph. D. in Reliability Engineering from the University of Arizona, which he attended from 1995 to 1999. He received his B.S. in 1983 and M.S in 1986 in Heat Energy Engineering, both from Hauzhong University of Science and Technology, China.|
|Date||Jan 22nd, 2015|
|Topic||Packaging Driven Reliability in High Voltage Packages|
|Abstract||High-voltage packages are used in a large number of areas in industrial (motor controls, Smart Grid, Smart Metering, microinverters), medical (defibrillators, electro cardiographs), telecom (phone modems, Ethernet/PoE), consumer (plasma displays, electronic gaming), and computer applications (power supplies, isolated I/O). Such packages present unique problems that need to be addressed to meet high-voltage requirements. This talk will review the aspects of high voltage design (e.g., creepage, clearance, tracking and comparative tracking index), and discuss some of the challenges from thermal management, humidity effects, to parasitic currents and breakdown voltage degradation.|
|Speaker||Dr. Luu Nguyen, Texas Instruments Inc.|
|Date||January 15, 2015|