IEEE Santa Clara Valley 
Solid State Circuits Society

Past Event

• April 17, 2008:   Our speaker was Raul-Adrian Cernea, (SanDisk Corporation), and the topic of his presentation was   "Nonvolatile Erasable Flash Nand Memories"

Abstract

Examination of NAND memories in general as well as the latest architecture accomplishments, based on three 2008 ISSCC papers jointly presented by SanDisk and Toshiba, are the subjects of this presentation. NAND Flash cell reside at the core of various types of memory cards. This memory cell represents the latest technological achievement when low cost and high performance are of concern. The basics of the erase and program operations are presented and the NAND chain functionality is explained. All Bit Line (ABL) access has multiple advantages when higher programming throughput is targeted and it was made possible by adopting "current sensing" contrary to a "conventional" voltage sensing scheme. General chip architecture is presented and a double size data buffer is found to be necessary for all bit line operation, while the area increase is a disadvantage. Changes are necessary to counterbalance the area increase. Hierarchical column architecture is of foremost importance. Optimization of other circuits is also helping. A different type of charge pump is one such example brought to attention. Fast data in and data out access rate are essential, and some ways of boosting them are mentioned, including a new redundancy scheme. A very important method of cost reduction is multiple level encoding. Single level versus multiple level encoding is discussed and the latest three bit per cell circuit is presented. Some algorithms that made it possible are shown. The performance drop is also pointed out. Energy saving is another topic of the presentation.

Presentation ends with conclusions and acknowledgements.

Raul-Adrian Cernea received the MS degree in Electronics and Engineering Physics from the Polytechnic Institute of Bucharest in 1972. From 1972 to 1984 he worked at the Research Institute for Electronic Components in Bucharest, Romania. From 1984 to 1990 he worked for SEEQ Technology, Milpitas, California, first as reliability engineer and later as design engineer. In 1990 he joined SanDisk where he led the NOR Flash design. Since 2000 he has been working on NAND Flash memories.

From 1989 to 2008 Mr. Cernea has coauthored numerous papers presented at ISSCC, CICC and VLSI Symposium. His fundamental paper "A 1Mb flash EEPROM", presented at IEEE International Solid-State Circuits Conference in February 1989 (ISSCC Proceeding vol. XXXII, pp. 138 - 139, and 316), has been cited in numerous papers in the years following.

Berkeley Professor Chenming Hu has included it in 1991 IEEE Press anthology "Nonvolatile Semiconductor Memories -- Trans. Technologies, Design, and Applications"

Adrian Cernea is an Engineering Fellow at SanDisk. He holds more than 100 US patents and has twice received the company "Patent of the Year" award.

SSC Technical meetings of SCV are typically held on The THIRD Thursday of each month at:

National Semiconductor Building E Auditorium
2900 Semiconductor Dr., Santa Clara, CA 95051   Directions