Abstract
This presentation describes circuit technologies for multi-core microprocessor design with specific examples from 90nm and 65nm Intel dual-core processors. We review cache hierarchy options for multi-core processors, as well as cache power reduction techniques using sleep and shut-off modes. Extensive use of long channel devices reduces sub-threshold leakage in non-timing critical paths. Multi-core clock distribution requires careful synchronization across cores, as well as sparse distribution networks over the caches to reduce power consumption. We review packaging options for multi-core processors, design-for-test and manufacturing features, as well as power and thermal management techniques.
Biography
Stefan Rusu (M’85-SM’01) received the MSEE degree from the Polytechnic Institute in Bucharest, Romania. He first joined Intel Corp. in 1984 working on data communications integrated circuits. In 1988 he joined Sun Microsystems working on microprocessor design with focus on clock and power distribution, packaging, standard cell libraries, CAD and circuit design methodology. He re-joined Intel Corp. in 1996 working on the clock and power distribution, cell library, I/O buffers and package for the first Itanium® processor. He is presently a Senior Principal Engineer in Intel's Enterprise Microprocessor Group leading the technology and special circuits design team for the Xeon® Processors Family. His technical interests are high-speed clocking, power distribution, I/O buffers, power and leakage reduction, and high-speed circuit design techniques. Stefan has authored or co-authored more than 70 papers on VLSI design methodology and microprocessor circuit technology. He holds 25 U.S. patents with several more pending. He is a member of the Technical Program Committee for ESSCIRC, A-SSCC and SoC conferences and an Associate Editor of the IEEE Journal of Solid-State Circuits.
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