Abstract
Pacemakers were first introduced in the 1950s, with only few transistors used in the device. Technology has advanced and there are over tens of millions of transistors in today?s implantable pacemaker system. A cardiac pacemaker is used to treat bradyarrhythmia (a heart rate that is too slow). This device monitors the heart's rate and rhythm, and provides electrical stimulation when the heart does not beat or beats too slowly. It is typically small in size, often less than an ounce in weight, and less than two inches wide. Once implanted inside the body, the pacemaker's presence is nearly invisible to the eye. Within the Pacemaker device, there is (1) the integrated circuit and (2) a battery. The IC is a full custom mixed-signal sub-micron SOC (system-on-chip) containing all the circuitry necessary to operate a sophisticated device. It monitors the heart?s rate and provides stimulation when necessary.
Low power consumption is crucial for pacemaker IC. The fundamental goal is to provide a life span of up to 10 to 12 years. In this presentation, a single-chip, very-low-power interface IC used in implantable pacemaker systems is discussed. Many low power analog/digital design techniques have been utilized. A large amount of analog and digital circuitries have been integrated. It contains low-noise amplifiers, filters, ADCs (~280nW), battery management system, high voltage charge pump (~400nW), high voltage D/A pulse generators, MEMS sensors and interface circuits (~120nW), programmable logic and timing control. A few new circuit techniques are proposed to achieve nano-power circuit operations for sub-micron CMOS process. For example, sub-threshold transistor designs and switched-capacitors circuits are widely used in the analog domain, and a large amount of clock-gating are used in the digital domain. The IC occupies 49mm2, is fabricated in a CMOS multi-Vt process and consumes 8mW on average from a single 2.8V supply.
Biography
Louis S Y Wong received the B.E. and 1st class Honours degree from The University of Adelaide, Australia, and the Ph.D. degree in electrical engineering from The University of New South Wales, Sydney Australia. During his Ph.D. and research program, he won The Australia Postgraduate Research Award and The IRE in Microelectronics.
In 1994-1996, he was with CSC Australia as a firmware engineer developing real-time embedded software for a defense combat system project. He then was with Cochlear Australia from 1997-2000 as a senior design engineer, where he was involved in research and development for a low-power mixed-signal single-chip-solution for bionic ear implant devices. In 2000, he joined St. Jude Medical in Sunnyvale. He is currently a mixed-signal Design Manager and a Senior Principle Design Engineer, where he is responsible for designing the next generation pacemaker ICs. Dr Wong was also a part time instructor in the San Jose State University, teaching a CMOS IC design course.
His research area includes low-voltage low-power sub-threshold analog/mixed-signal and digital designs. He has filed and published numerous patents and papers in this area, such as with ISSCC, CICC, JSSC, and ISLPED. His design experience includes very low power A/D converters, battery power management systems, high-voltage charge pump in CMOS technology, radiation-hardened logic and memory, low power IO cells, low power PLL, and lowest voltage D/A converter (0.9V) ever reported.
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