IEEE Santa Clara Valley 
Solid State Circuits Society



Previous Event

Abstract

Low density parity check (LDPC) codes have received significant attention due to their superior error correction performance, and have been considered by emerging communication standards such as 10 Gigabit Ethernet (10GBASE-T), digital video broadcasting (DVBS2), WiMAX (802.16e), Wi-Fi (802.11n) and WPANs (802.15.3c). Due to the codes' inherently irregular and global communication patterns, high-speed systems that require many processing nodes typically suffer from large wire dominated circuits with low clock rates. The recently introduced Split-Row Threshold decoding algorithms and architectures increase parallelism, significantly reduce wire interconnect complexity, and have a small increase in bit error rate compared to the standard MinSum decoding algorithm. Several Multi-Split-Row Threshold decoders have been implemented in 65 nm CMOS for a (2048,1723) LDPC code compliant with the 10GBASE-T Ethernet standard. The impact of different levels of partitioning on error performance, wire interconnect complexity, decoder area, power dissipation and speed are investigated. A 16-way Split-Row Threshold decoder occupies 5.2 mm^2, runs at 173 MHz, delivers a throughput of 32 Gbps, and dissipates 608 mW at 1.3 V and 11 decoding iterations. At 0.69 V it delivers 6.4 Gbps and dissipates 35 mW. Compared to a standard MinSum decoder implemented in the same technology and physical design flow, the presented chip is 3.5 times smaller, has a clock rate and throughput 10 times higher, is 3.9 times more energy efficient, and has an error performance degradation of only 0.22 dB.




Biography

Tinoosh Mohsenin received the B.S. degree in electrical engineering from Sharif University, Tehran, Iran, and the M.S. degree in electrical and computer engineering from Rice University, Houston, TX. She is currently pursuing the Ph.D. degree in electrical and computer engineering at the University of California, Davis. She is the designer of the Split-Row, Multi-Split, and Split-Row Threshold decoding algorithms and architectures for low density parity check (LDPC) codes. Her research interests include energy-efficient and high-performance signal processing and error correction architectures including multi-gigabit full-parallel LDPC decoders and many-core processor architecture design.





SSC Technical meetings of SCV are typically held on The THIRD Thursday of each month at:

National Semiconductor Building E Auditorium
2900 Semiconductor Dr., Santa Clara, CA 95051   Directions

Refreshments are provided at 6:00 PM and the talk typically starts at 6:30 PM.
  Donation requested to partially cover food cost Home