IEEE Santa Clara Valley 
Solid State Circuits Society

 

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Next generation telecommunication and data communication network equipment will begin deploying OC-768 fiber links at data rates up to 43Gb/s. By increasing data rates, network service providers benefit by obtaining lower management cost, reduced inventory overhead associated with many OC-(12/48/192) components, reduced rack space, and will have an overall lower operational budget. Initial OC-768 deployment is focused on short-reach applications, typically defined to be less than 2 kilometers. An example of a short-reach application would be the use of fiber to connect routers and switches within a data center or central office. A key component in enabling a short-haul optical link is an OC-768 optical transponder.

This talk describes the design, implementation, and testing of two key IC building blocks in an OC-768 optical transponder.

During the first half of the talk, we will describe a 40-43 Gb/s clock and data recovery IC with 1:16 demultiplexer that is compliant with the SFI-5 specification. The CDR operates from -5.2V and +1.8V supplies and dissipates 7.5W.

The second half of the talk presents a 40-43 Gb/s 16:1 multiplexer and clock multiplier unit with an SFI-5 compliant parallel data interface. The unit incorporates two chips, a 16:4 MUX and a 4:1 MUX/CMU, co-packaged in a ceramic package. The MUX/CMU meets all relevant ITU and OIF specifications, and dissipates 9W from -5.2, 1.8 and 3.3V supplies. All ICs were implemented in a 120GHz/100GHz (ft/fmax) SiGe technology. All ICs have been packaged and integrated into an OC-768 optical transponder, which in optical loopback test over 2km of fiber, shows a BER better than 1e-15 at 43Gb/s.

 

 Adrian Ong received the B.S. degree in electrical engineering from the University of California at Berkeley in 1992 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1993 and 1999, respectively. His doctoral research focused on the design of bandpass sigma-delta modulators for narrowband IF digitization. From 1998 to 2000,he was a Member of Techical Staff with Bell Laboratories, Lucent Technologies, Murray Hill, NJ, and a design engineer at Atheros Communications, Sunnyvale, CA. In August 2000, he joined Big Bear Networks, Sunnyvale, CA. His technical interests include the design of analog and mixed-signal circuits for wired and wireless communications and high-speed clock and data recovery circuits in SiGe and CMOS technologies.

 Derek K. Shaeffer received the BSEE degree from the University of Southern California in 1993, the MSEE degree from Stanford University in 1995 and the Ph.D. degree from Stanford University in 1999, for which he did early work in the field of CMOS RF, demonstrating the world's first CMOS GPS receiver. He is the author or co-author of six patents, eighteen papers and a book on CMOS RF design. He has worked professionally in the fields of test instrumentation, semiconductor memory, wireless and optical communications. From 1992 to 1997 he worked for Tektronix, Inc., where he did design work in spectrum analysis, precision A/D conversion and RF communications. In 1998 he joined Matrix Semiconductor, where he did work on next generation memory technologies. In 1999 he co-founded FreeSpace Communications, where he worked on last-mile broadband wireless access networks. Since 2001, he has been with Big Bear Networks, where his current work is in 10-Gb/s and 40-Gb/s optical communications circuits and systems.

 

SSC Technical meetings of SCV are held on The THIRD Thursday of each month at:
Cadence Building 5 which is located at 2655 Seely Ave, San Jose, 95134.  

Refreshments are provided at 6:00 PM and the talk typically starts at 7:00 PM.