IEEE Santa Clara Valley 
Solid State Circuits Society

This talk describes a low-power, high bit rate optical interconnect transceiver architecture suitable for large-scale integration in modern and future CMOS processes. The transceiver incorporates a 4-tap FIR TX in order to extend effective VCSEL bandwidth for a given reliability level. A low-voltage integrating and double-sampling sense-amplifier-based receiver provides adequate sensitivity in a power efficient manner by eliminating the conventional high-gain transimpedance input stage. Further reduction in power and area is obtained with a dual-loop clock and data recovery (CDR) system with baud rate phase detection. Fabricated in 1V 90nm CMOS, the transceiver achieves 16Gb/s operation while consuming 129mW and occupying 0.105mm2.

Samuel Palermo (S'98-M'07) received the B.S. and M.S. degree in electrical engineering from Texas A&M University, College Station, TX in 1997 and 1999, respectively. He is currently wrapping up his Ph.D. degree from Stanford University, Stanford, CA.

From 1999 to 2000, he was with Texas Instruments, Dallas, TX, where he worked on the design of mixed-signal integrated circuits for high-speed serial data communication. He is currently at Intel Corporation, Hillsboro, OR, working on high-speed optical and electrical I/O architectures. His research interests include high-speed electrical and optical links, clock recovery systems, and techniques for device variability compensation.