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IEEE Santa Clara Valley
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Abstract
With mobile devices becoming more powerful and including more storage than ever before, new applications are emerging that require fast wireless data transfers while consuming very low power. This talk will present the key design techniques and challenges in implementing a low power 90nm CMOS 60GHz transceiver that includes RF, LO, PLL and BB integrated into a single chip. With a 1.2V supply the chip consumes 170mW while transmitting 10dBm and 138mW while receiving. Data transmission up to 5Gbps on each of I and Q channels has been measured, as has data reception over a 1m wireless link at 4Gbps QPSK with less than 10-11 BER.
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SSC Technical meetings of SCV are typically held on The THIRD Thursday of each month at: National
Semiconductor Building E Auditorium Donation requested to partially cover food cost Home |