IEEE Santa Clara Valley 
Solid State Circuits Society



Past Event

  • June 28, 2007:   Our speaker was   Mr. Dennis Fischette, BSc.Phys. (AMD), and the topic of his presentation was " First Time, Every Time. Practical Advice for Phase-Locked Loop Design Success in a Modern CMOS World. "

Abstract

The phase-locked loop (PLL) is an often feared and misunderstood beast. Black-box designs from IP vendors are integrated on-chip with little understanding of the PLL's sensitivities to process and digital noise. Inexperienced designers read the latest literature and try to hit a "home run" with their first PLL. Ignorance of the PLL's internal workings leads to impossible-to-meet specs and inadequate test features. The result? Costly silicon spins, hapless debug efforts, and missed product windows. This presentation provides a practical exploration of real-world PLL design for clock generation and high-speed IO (e.g. PCI-Express) with emphasis on 45nm and 65nm designs. Topics include
- achieving a real physical feel for feedback stability
- common circuit implementations and how they can go horribly wrong
- avoiding late nights in the lab with inexpensive test and debug features
- defining, isolating, and measuring PLL jitter
- creating a tape-out checklist to ensure first-pass success
- subtle design implications of high-speed IO clocks
- real-world failures and successes.

Biography

Dennis Fischette designs mixed-signal circuits at Advanced Micro Devices in Sunnyvale, CA. His technical interests include PLL and DLL design, clock-and-data recovery, circuit analysis software, and high-speed IO circuits. He is a member of the IEEE Distinguished Lecturer program as well as the CICC Technical Program Committee. He was a member of the ISSCC Technical Program Committee from 2001-2006.

He graduated from Cornell University, Ithaca, NY, with Physics BSc in 1986. Before seeking fame and fortune in Silicon Valley, he pursued graduate studies in the History of Science at the University of California, Berkeley.

Dennis is known to "toot his own horn" all over the SF Bay Area as a trombonist with several jazz ensembles. He recently toured China and Vietnam with the SFBayJazz big band.


SSC Technical meetings of SCV are typically held on The THIRD Thursday of each month at:

National Semiconductor Building E Auditorium
2900 Semiconductor Dr., Santa Clara, CA 95051   Directions

Refreshments are provided at 6:00 PM and the talk typically starts at 6:30 PM.
  Donation requested to partially cover food cost Home