With WLAN explosion the RFIC’s have become a very
important solid-state design activity.
This presentation describes a CMOS transceiver fully
compliant with IEEE 802.11a standard in the Unlicensed
National Information Infrastructure (U-NII) band at
5.15-5.35 GHz.
It uses direct conversion architecture in order to
reduce the chip area and power consumption.
The transceiver contains the receiver with AGC, the
transmitter with programmable output power and
reconstruction filters and the frequency synthesizer.
It achieves a sensitivity of -69 dBm and an error
vector magnitude of -29.3 dB for 64QAM OFDM signals at
54Mbit/s data rate. Frequency synthesizer uses
single-sideband mixing technique for LO generation to
avoid frequency pulling.
Realized in 0.18-um CMOS and operating from 1.8 V
single supply, the chip consumes 171 mW in receive
mode and 135 mW in transmit mode.
Pengfei Zhang (M’97) received the B.S., M.S. and Ph.D.
degrees in Electrical Engineering from Tsinghua
University, Beijing, China, in 1988, 1990 and 1994,
respectively.
From 1994 to 1996, he was a Post-Doctoral Scientist of
the Electrical Engineering Department at University of
California, Los Angeles, CA, where he did research on
numerical simulation of SOI devices. From 1996 to
1999, he was with Rockwell Semiconductors, Inc,
Newport Beach, CA, where he worked on advanced process
technology development for 56K-Modem. From 1999 to
2000, he was with Fujitsu Microelectronics, Inc., San
Jose, CA. He worked on design methodology for signal
integrity in mixed-signal IC’s and RFIC design for
wireless networking applications. Since 2000, he has
been with RF Micro Devices, San Jose, CA (formerly
Resonext Communications, Inc), where he is Design
Manager of RFIC group at the WLAN Division, working on
transceiver chip development for multi-standard
applications. His research interests are in the area
of integrated circuits for wireless communications.
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