Abstract
The design and implementation of an IEEE 802.11a/b/g wireless LAN
System-on-Chip (SoC) for low-power embedded applications is presented.
Fabricated in a 0.18um CMOS technology, the IC integrates the RF
transceiver, digital PHY processor and media access controller, CPU,
power management unit and host interface. For a 54Mb/s 64-QAM OFDM
signal, the overall 5GHz and 2.4GHz receiver sensitivity is -73dBm and
-76dBm, respectively. The 5GHz and 2.4GHz transmit EVM is -27dB and
-27.5dB, respectively, at an output power of -4dBm. The total SoC
power dissipation is under 425mW in either transmit or receive modes
and typically under 300uW in sleep mode.
Biography
Lalit Nathawad received the B.A.Sc. degree in engineering physics
from Simon Fraser University, Burnaby, Canada, in 1997,
and the M.S. and Ph.D. degrees in electrical engineering from
Stanford University, Stanford, CA, in 2000 and 2004, respectively.
His doctoral research focused on the design of high-speed
CMOS analog-to-digital converters.
During the summer of 2000, he interned with National Semiconductor,
Santa Clara, CA, where he worked on a wideband sample-and-hold circuit
for pipeline A/D converters.
Since January 2004, he has been with Atheros Communications, Irvine, CA
where he is a senior analog design engineer involved in the design
of RF transceivers, frequency synthesizers, data converters
and other mixed-signal circuits for wireless communication products.
Abstract
A single-chip CMOS PHS cellphone, fabricated in a 0.18um CMOS process,
implements all handset functions including radio, voice, audio, CPU,
and digital interfaces.
The IC has +4dBm EVM-compliant transmit power, -106dBm receiver sensitivity,
and 15us synthesizer settling time.
Biography
William W. Si (M'99) received the B.S., M.S., and Ph.D. degrees in electronics
engineering in Tsinghua University, Bejing, China in 1988, 1990 and 1994.
He also received the M.S. degree in electrical engineering from
Stanford University in 1996.
He joined Atheros Communications in February 2001, where he has designed
phase-locked loops, A/D and D/A converters, RF transceivers and integer-N
and fractional-N RF frequency synthesizers for wireless LAN and PHS
cellular phone products.
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