Abstract
Talk #1 - Sotirios Limotyrakis: An 802.11n 2x2 MIMO radio in 0.13um CMOS
An 802.11n-draft-compliant 2x2 2-stream MIMO radio SoC incorporates two
dual-band RF transceivers, analog baseband filters, data converters,
digital PHY and MAC, and a PCI Express interface. Implemented in a 0.13-um
CMOS, it occupies 36mm^2. For 2.4GHz/5GHz, the receive chain NF is 4dB/6dB,
and the transmit EVM is -34dB/-30dB at -5dBm output power. Details will be
presented on the RF and baseband sections of the chip.
Talk #2 - David Weber: A Bluetooth v2.1 radio in 0.13μm CMOS
A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced
Data Rates is implemented in standard 0.13μm CMOS technology. Radio architectures
have been chosen that minimize the area of the analog and RF circuits. This
design features a polar transmitter, a two-point modulated fractional-N
synthesizer, a 500kHz IF receiver with first order low-pass analog filtering,
and a ΔΣ ADC. The total SoC die area is 9.2mm2 with only 3.0mm2 used for analog
and RF circuits. The basic-rate radio power consumption is 28mA in receive and
30mA in transmit.
Biographies
Sotirios Limotyrakis was born in Athens, Greece, in 1971. He received the B.S.
degree in electrical engineering from the National Technical University of
Athens in 1995 and the M.S. and Ph.D. degrees in electrical engineering from
Stanford University in 1997 and 2005.
In the summer of 1993, he worked at K.D.D. Corporation, Saitama R&D Labs, Japan,
on the design of communication protocols. During the summers of 1996 and 1997,
he worked with the RF design group at the Texas Instruments Inc. R&D center in
Dallas, Texas. He focused on LNA, low phase noise oscillator design, and GSM
mobile unit transmit path architectures. In November 2004 he joined Atheros
Communications, Inc., as a Member of Technical Staff. His current research interests
include the design of mixed-signal and RF circuits for high speed data conversion
and broadband communications.
In 1995, Dr. Limotyrakis was awarded the W. Burgess Dempster Memorial Fellowship
by the School of Engineering at Stanford University. He is the corecipient of the
2004 IEEE Beatrice Winner award for editorial excellence and the recipient of the
2004 Analog Devices outstanding student designer award.
David Weber is a manager in the analog design group at Atheros Communications.
He received a B.S.E.E. degree from the University of New Hampshire in 1995, and
in 1996 he received an M.S.E.E. degree from Stanford University. From 1996 to 1999
he worked at Hewlett Packard as a hardware design engineer, designing RF power
modules for digital cellular phones. In 2000, he joined Atheros Communications as
an analog design engineer, where he designed a variety of circuits for wireless
LAN SoCs, including power amplifiers, frequency synthesizers, and data converters.
In 2004 he descended into management, and now leads the development of CMOS radios
for WLAN, Bluetooth, and other technologies. He has been a member of the IEEE
since 1993.
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