Abstract
Moore's Law scaling has led to ultra-short channel length devices that, while giving multi-GHz performance, present a host of new challenges. This talk will look at a range of "other" issues that face compact modeling of nano-meter scale technology. This will include a growing list of parasitic effects related to: gate leakage, substrate coupling and thermal limitations. There are also issues of intrinsic device scaling; there is growing momentum for open source, high-level specifications, for models that facilitate new paradigms for model portability. This paradigm shift will be considered for both intrinsic and parasitic modeling needs.
Biography
Professor Robert Dutton attended the University of California, Berkeley where he received the BS, MS and Ph.D. degrees in Electrical Engineering. He joined the faculty of Electrical Engineering at Stanford University where he has served as Director of Research at the Center for Integrated Systems (CIS) and is currently Director of the Integrated Circuits Laboratory (ICL). His research career has focused on computer simulation of integrated circuit technology, including both models of the IC fabrication processes and electrical behavior of new transistor and circuit structures. The simulation tools and software pioneered by Prof. Dutton's group has been universally adopted by industry and used prolifically in support of technology development. In 1980 he founded the first commercial Technology Computer Aided Design (TCAD) company, Technology Modeling Associates, that became a public company in 1996 (TMAI, NASDAQ), which merged with Avanti and is now part of Synopsys. He had industrial experience at: Fairchild Semiconductor, Bell Labs, IBM, Hewlett-Packard and Matsushita. His awards include: IEEE Fellow, J.J. Ebers and Jack A. Morton Awards, Member of the National Academy of Engineering (NAE) and the Recipient of the Computers and Communications (C&C) Prize, Japan.
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