IEEE Santa Clara Valley 
Solid State Circuits Society

 

Previous Events

The power amplifier (PA) is an integral part of any wireless communications system.  Using CMOS technology for power amplification is desirable because a CMOS PA can be combined with other radio functions in a cost-effective integrated transceiver. However implementing efficient power amplifiers in a main-stream digital CMOS technology remains a major challenge.  This talk starts with a brief tutorial on CMOS power amplifier design.  In addition, three PA design case studies are presented: a nonlinear 32dBm, 800MHz PA with 42% power-added efficiency; a linear 18dBm, 5GHz PA for IEEE 802.11a wireless LAN; and a linearization IC for North American digital cellular that improve efficiency from 36 to 49% using envelope elimination and restoration.

Biography: David Su joined Atheros in February 1999, where he is currently the director of analog/RF IC design. He spent 10 years at Hewlett-Packard Company (IC Business Division and HP Labs) designing CMOS mixed-signal, analog, and RF ICs. He has also been a consulting assistant professor at Stanford University since 1997. Dr. Su holds a Ph.D. in electrical engineering from Stanford University as well as M.E. and B.S.E.E. degrees from the University of Tennessee at Knoxville.

 

SSC Technical meetings of SCV are held on The THIRD Thursday of each month at:
Cadence Building 5 which is located at 2655 Seely Ave, San Jose, 95134.  

Refreshments are provided at 6:00 PM and the talk typically starts at 7:00 PM.