21st Canadian Conference on Electrical and Computer Engineering
Home Call For Papers Committee Registration Sponsors Awards Banquet Student Activities
Conference Program - Quick Glance
Full Technical Program Schedule
Tutorials Plenaries Keynotes Technical Sessions Schedule
Author's Information
Author's Guide    /     Paper Kit
Hotel & Travel Information
Hotel Reservations    /     Hotel Directions    /     Air Travelers Tips
Flight Booking Discount - West Jet Airlines
Conference Secretariat
CCECE 2008
IEEE Canada
PO Box 63005
University Postal Outlet
102 Plaza Drive
Dundas, ON, L9H 4H0
Ph/Fax: (905) 628 - 9554 Email:

Author's Guide

Paper Kit


French / Français



to the 21th annual
IEEE Canada Conference

read our history
The Wonders of Technology May 4-7, 2008
Sheraton Fallsview
Niagara Falls
Ontario, Canada

Tutorial A: High-Performance Chip-to-Chip Signaling

Sunday Morning, May 4
9 a.m. - 12 p.m.
Ontario Room

Presented by

Prof. Tony Chan Carusone - Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada


High-performance chip-to-chip signaling is a challenging requirement of many modern VLSI systems and with ITRS predictions of 160-Gb/s serial I/O and 40-Gb/s parallel I/O links by 2016 it is likely to remain so. There has recently been a proliferation of signaling standards such as PCI Express, XAUI, RapidIO, Interlaken, and others making it difficult for practicing engineers and researchers to keep up. This tutorial presents the fundamentals of chip-to-chip signaling enabling attendees to understand and meet the requirements of these technologies. The most pressing research challenges in chip-to-chip signaling are also covered, so that by the end of the session attendees are up to speed with the state-of-the-art. First, the requirements and specifications of chip-to-chip links are introduced. Particular attention is paid to signal integrity. Modeling and simulation methodologies that include the effects of trace losses, link discontinuities, clock jitter, and noise are presented enabling attendees to accurately estimate bit error rates over complex links. We will then proceed to circuit architectures for transmitters and receivers. The presenter is an active researcher in highspeed equalization and clock recovery, so these will be areas of focus. Any engineers working with multi-Gb/s digital signals will benefit by gaining an understanding of signal specifications, signal integrity, and clocking architectures. Chip-to-chip signaling researchers will gain insights into advanced modeling techniques and high-speed equalization and timing recovery architectures.

Presenter's Biography

Anthony Chan Carusone received the Ph.D. from the Department of Electrical and Computer Engineering at the University of Toronto in 2002. In 2001 he joined the faculty at the University of Toronto where he is currently an Associate Professor. In 2002, Dr. Chan Carusone was named an Ontario Distinguished Researcher and Canada Research Chair in Integrated Systems. He co-authored the best paper at the 2005 Compound Semiconductor Integrated Circuits Symposium and the best student paper at the 2007 Custom Integrated Circuits Conference. He is a past chair of the Analog Signal Processing Technical Committee for the IEEE Circuits and Systems Society, a member of the technical program committee for the Custom Integrated Circuits Conference, and Deputy Editor-in-Chief for the IEEE Transactions on Circuits and Systems II: Express Briefs. He is also an occasional consultant to industry in the area of highspeed transceiver integrated circuits.

Back to the tutorials page
Retour au page des sťances

Sponsored by IEEE Canada and the Sections of Central Canada
by the

ecommerce web site